公开(公告)号：US20160357571A1

公开(公告)日：2016-12-08

申请号：US14731216

申请日：2015-06-04

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F9/44 ,  G06F13/362

CPC classification number: G06F9/4401 ,  G06F13/362

Abstract: Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.

Abstract translation: 本公开的实现涉及通过将复位控制器连接到复位控制器总线或其他类型的通用总线来实现微处理器或其他类型的计算系统的复位控制器的系统和/或方法。 通过复位总线，用于产生系统的复位序列的复位控制器信号可以通过总线传送到系统的组件，而不是利用组件和复位控制器之间的直接线连接。 构成复位总线的导线然后可以运行到在复位序列期间重新启动的微处理器设计的一个或多个组件。 这些部件中的每一个还可以包括复位控制器电路，其被设计为从复位控制器接收复位控制信号并对信号进行解码以确定接收到的信号是否适用于该部件。

公开(公告)号：US09460013B2

公开(公告)日：2016-10-04

申请号：US14479191

申请日：2014-09-05

Applicant: Oracle International Corporation

Inventor： David Richard Smentek ,  Ali Vahidsafa ,  Venkatram Krishnaswamy ,  Thirumalai Swamy Suresh

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F2212/62 ,  G06F2212/621

Abstract: A method for removal of an offlining cache agent, including: initiating an offlining of the offlining cache agent from communicating with a plurality of participating cache agents while a first transaction is in progress; setting, based on initiating the offlining, an ignore response indicator corresponding to the offlining cache agent on each of the plurality of participating cache agents; offlining, based on setting the ignore response indicator, the offlining cache agent; and ignoring, based on setting the ignore response indicator, a first response to the transaction from the offlining cache agent.

Abstract translation: 一种用于去除最终缓存代理的方法，包括：在第一次交易进行期间，发起关闭高速缓存代理与多个参与高速缓存代理的通信; 基于发起所述离线，设置与所述多个参与高速缓存代理中的每一个上的所述高速缓存代理相对应的忽略响应指示符; 根据设置忽略响应指示符，即关闭缓存代理; 并且基于设置忽略响应指示符忽略来自所述高速缓存代理的对所述事务的第一响应。

公开(公告)号：US20160070646A1

公开(公告)日：2016-03-10

申请号：US14479191

申请日：2014-09-05

Applicant: Oracle International Corporation

Inventor： David Richard Smentek ,  Ali Vahidsafa ,  Venkatram Krishnaswamy ,  Thirumalai Swamy Suresh

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F2212/62 ,  G06F2212/621

Abstract: A method for removal of an offlining cache agent, including: initiating an offlining of the offlining cache agent from communicating with a plurality of participating cache agents while a first transaction is in progress; setting, based on initiating the offlining, an ignore response indicator corresponding to the offlining cache agent on each of the plurality of participating cache agents; offlining, based on setting the ignore response indicator, the offlining cache agent; and ignoring, based on setting the ignore response indicator, a first response to the transaction from the offlining cache agent.

Abstract translation: 一种用于去除最终缓存代理的方法，包括：在第一次交易进行期间，发起关闭高速缓存代理与多个参与高速缓存代理的通信; 基于发起所述离线，设置与所述多个参与高速缓存代理中的每一个上的所述高速缓存代理相对应的忽略响应指示符; 根据设置忽略响应指示符，即关闭缓存代理; 并且基于设置忽略响应指示符忽略来自所述高速缓存代理的对所述事务的第一响应。

公开(公告)号：US20150377960A1

公开(公告)日：2015-12-31

申请号：US14316468

申请日：2014-06-26

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Roger Charles Mistely

IPC: G01R31/3177

CPC classification number: G01R31/31922 ,  G01R31/318552 ,  G01R31/318563 ,  G01R31/318594 ,  G01R31/31908 ,  G06F11/2236 ,  G06F11/263

Abstract: Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced.

Abstract translation: 本公开的实现涉及用于通过每个域中的时钟脉冲的受控顺序来以不同频率进行微处理器设计的不同时钟域的同时转换测试的装置和/或方法。 通常，微电子设计利用与设计的每个时钟域相关联的测试控制电路来进行时钟域的同时转换测试。 与微电子设计的每个时钟域相关联的测试控制电路还允许测试设备延迟特定时钟域内的测试。 通过延迟特定时钟域内的测试，可以同步各种时钟域的测试。 通过这些测试程序，进行微电子设计的ATPG测试所需的时间可能会大大降低。

公开(公告)号：US10528351B2

公开(公告)日：2020-01-07

申请号：US15632567

申请日：2017-06-26

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/00 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F3/06 ,  G06F11/20 ,  G06F9/38 ,  G06F9/48

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US09509317B2

公开(公告)日：2016-11-29

申请号：US13755056

申请日：2013-01-31

Applicant: Oracle International Corporation

Inventor： Robert P Masleid ,  Ali Vahidsafa

IPC: H03L7/00 ,  H04L7/02 ,  H04L25/05 ,  H04L7/00

CPC classification number: H03L7/00 ,  H04L7/005 ,  H04L7/02 ,  H04L25/05

Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

Abstract translation: 公开了一种用于亚稳定性分辨率的旋转同步器。 同步器包括多个M + 1个锁存器，每个锁存器被耦合以通过公共数据输入来接收数据。 所述同步器还包括多路复用器，其具有N个输入端，每个输入端分别被耦合以从所述M + 1锁存器中对应的一个锁存器的输出端接收数据，以及输出端，其中，所述多路复用器被配置为选择其输入之一耦合到所述输出端 。 控制电路被配置为使得多路复用器响应于N个连续时钟脉冲顺序地选择M + 1个锁存器的输出，并且还被配置为使得M + 1锁存器顺序地锁存通过公共数据输入接收到的数据。

公开(公告)号：US09404967B2

公开(公告)日：2016-08-02

申请号：US14535647

申请日：2014-11-07

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G01R31/02 ,  G01R31/317

CPC classification number: G01R31/31726 ,  G01R31/31713 ,  G01R31/31727 ,  G01R31/318544

Abstract: Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.

Abstract translation: 本公开的实现涉及用于在数字集成电路的结构测试期间混合高速和低速时钟信号以提高测试精度和效率的装置和/或方法。 具体地，该装置和/或方法允许测试装置通过释放低速时钟信号的一个或多个时钟周期来执行电路的卡位测试。 此外，不必重置电路的测试，电路的高速测试可以由测试装置进行。 在一个实施例中，通过激活与电路设计相关联的模式信号来进行速度测试，其指示从内部时钟信号到要释放的电路的一个或多个时钟周期。 测试设备可以以低速时钟信号返回卡位测试，或使用高速内部时钟信号继续进行高速测试。

公开(公告)号：US20160210255A1

公开(公告)日：2016-07-21

申请号：US14598640

申请日：2015-01-16

Applicant: Oracle International Corporation

Inventor： Thomas Wicki ,  David Smentek ,  Sumti Jairath ,  Kathirgamar Aingaran ,  Ali Vahidsafa ,  Paul Loewenstein

IPC: G06F13/40 ,  G06F11/22 ,  G06F11/30

CPC classification number: G06F13/4022 ,  G06F11/221 ,  H04L12/00 ,  H04L12/4625

Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

Abstract translation: 公开了一种系统，其中系统可以包括多个总线开关和多个处理器。 每个处理器可以耦合到每个总线开关。 每个处理器可以被配置为启动数据到给定总线开关的传输，并检测到给定总线开关的相应链路是否不可操作。 响应于检测到不可操作的链接到第一总线交换机，给定处理器可以进一步被配置为经由至少第二总线交换机向至少一个其他处理器发送通知消息，并且从一个第二总线交换机去除对应于不可操作链路的路由信息 首先注册 响应于从给定处理器接收到通知消息，至少一个其他处理器可以被配置为从第二寄存器去除对应于不可操作链路的附加路由信息。

公开(公告)号：US20160195894A1

公开(公告)日：2016-07-07

申请号：US14590748

申请日：2015-01-06

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0033

Abstract: Implementations of the present disclosure involve an apparatus and/or method for adjusting a counter in a computing system to account for drift of the counter value over time compared to another counter of the system. In particular, a processor of the computing system that includes a local counter component may access a counter component of another processor of the system, referred to as the reference counter. By comparing the value of the reference counter to the local counter, the processor may determine any drift that may have occurred over a period of time in the local counter. The calculated drift, or counter error, may be converted into one or more adjustments to the local counter to synchronize the local counter with the reference counter. In one embodiment, the adjustment to the local counter includes increasing the rate at which the local counter is incremented for a period of time.

Abstract translation: 本公开的实现涉及用于在计算系统中调整计数器的装置和/或方法，以考虑与系统的另一个计数器相比计算值随时间的漂移。 特别地，包括本地计数器组件的计算系统的处理器可以访问被称为参考计数器的系统的另一个处理器的计数器组件。 通过将参考计数器的值与本地计数器进行比较，处理器可以确定本地计数器中可能在一段时间内发生的漂移。 计算的漂移或计数器错误可以转换为本地计数器的一个或多个调整，以使本地计数器与参考计数器同步。 在一个实施例中，对本地计数器的调整包括增加本地计数器递增一段时间的速率。

公开(公告)号：US20160147534A1

公开(公告)日：2016-05-26

申请号：US14549742

申请日：2014-11-21

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30145 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/2028 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2201/805 ,  G06F2212/452 ,  Y02D10/13

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Abstract translation: 公开了一种装置，其中装置可以包括多个芯，包括第一芯，第二芯和第三芯，以及耦合到第一芯的电路。 第一核可以被配置为处理多个指令。 电路可以被配置为检测第一核心停止提交多个指令的子集，并且向第二核心发送指示第一核心停止提交子集的指示。 第二核心可以被配置为响应于接收到指示而禁止第一核心进一步处理该子集的指令，并且响应于禁用第一核心将数据从第一核心复制到第三核心。 第三核可以被配置为依赖于数据来恢复处理该子集。