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    Systems and Methods for Retiring and Unretiring Cache Lines
    11.
    发明申请
    Systems and Methods for Retiring and Unretiring Cache Lines 有权
    退出和退出缓存行的系统和方法

    公开(公告)号：US20150039938A1

    公开(公告)日：2015-02-05

    申请号：US14486776

    申请日：2014-09-15

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Ramaswamy Sivaramakrishnan ,  Ali Vahidsafa ,  Aaron S. Wynn ,  Connie W. Cheung

    IPC: G06F11/07 ,  G06F12/08

    CPC classification number: G06F11/0793 ,  G06F9/30 ,  G06F9/30047 ,  G06F11/073 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1032

    Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

    Abstract translation: 本文描述的系统和方法可以提供用于退出“不良”高速缓存位置（例如，与持续错误相关联的位置）的刷新退出指令，以防止其对任何进一步访问的分配，以及用于撤销先前退休的高速缓存位置的刷新指令 。 这些指令可以被实现为处理器的硬件指令。 它们可以由以超级特权状态执行的进程执行，而不需要使任何其他进程停顿。 刷新 - 退出指令可以原子地刷新由检测到的高速缓存错误所牵连的高速缓存行，并设置锁定位以禁用对应的高速缓存位置的后续分配。 flush-unretire指令可以原子地刷新已识别的高速缓存行（如果有效）并清除锁定位以重新启用高速缓存位置的后续分配。 这些指令的编码中的各个比特可以根据物理高速缓存结构来标识要退休或未退出的高速缓存位置。

    BROADCAST CACHE COHERENCE ON PARTIALLY-ORDERED NETWORK
    12.
    发明申请
    BROADCAST CACHE COHERENCE ON PARTIALLY-ORDERED NETWORK 有权
    BROADCAST CACHE关于部分网络的协调

    公开(公告)号：US20140281237A1

    公开(公告)日：2014-09-18

    申请号：US13830967

    申请日：2013-03-14

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Paul N. Loewenstein ,  Stephen E. Phillips ,  David Richard Smentek ,  Connie Wai Mun Cheung ,  Serena Wing Yee Leung ,  Damien Walker ,  Ramaswamy Sivaramakrishnan

    IPC: G06F12/08

    CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828

    Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.

    Abstract translation: 一种用于高速缓存一致性的方法，包括：通过部分有序请求网络（RN）的请求者缓存（RC）广播对多个从高速缓存的高速缓存线的对等（P2P）请求; 当P2P请求正在等待时，由RC接收和通过RN接收来自网关的高速缓存行的转发请求; 由所述RC接收所述转发请求后，从所述多个从属高速缓存中接收对所述P2P请求的多个响应; 在所述RC中设置所述高速缓存行的处理器内状态，其中所述处理器内状态还指定所述高速缓存行的处理器间状态; 以及在设置处理器内状态之后，在P2P请求完成之后，由RC发出对转发请求的响应; 以及响应于发出对所转发的请求的响应，由RC修改处理器内状态。

    Hardware accelerated data processing operations for storage data
    13.
    发明授权
    Hardware accelerated data processing operations for storage data 有权

    公开(公告)号：US10963295B2

    公开(公告)日：2021-03-30

    申请号：US15699027

    申请日：2017-09-08

    Applicant: Oracle International Corporation

    Inventor： John R. Feehrer ,  Milton Shih ,  Matthew Cohen ,  Kenneth Chan ,  Ramaswamy Sivaramakrishnan ,  Julia Harper ,  Peter Dunlap

    IPC: G06F9/48 ,  G06F21/60 ,  G06F11/07 ,  G06F13/42 ,  G06F11/10

    Abstract: A method and system for processing data are disclosed. A processor, in response to executing a software program, may write an entry in a work queue. The entry may include an operation, and a location of data stored in an input buffer, and a location in an output buffer to write processed data. The processor may also generate a notification that at least one entry in the work queue is ready to be processed. The data transformation unit may assign the entry to a data transformation circuit, and retrieve the data from the input buffer using the location. The data transformation unit may also perform to the operation on the retrieved data to generate updated data, generate a completion message in response to completion of the operation, and store the updated data in an output buffer. An interface unit may relay transactions between the processor and the data transformation unit.

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