公开(公告)号：US06924184B2

公开(公告)日：2005-08-02

申请号：US10394352

申请日：2003-03-21

申请人： Nigel G. Cave ,  Anna M. Phillips ,  Terry G. Sparks

发明人： Nigel G. Cave ,  Anna M. Phillips ,  Terry G. Sparks

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L23/48

CPC分类号： H01L21/76819 ,  H01L21/76802 ,  H01L21/76835

摘要： Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

摘要翻译： 通孔到晶体管的源极/漏极被制成具有非常均匀的深度，使得光致抗蚀剂厚度可以最小化，以减少与以最小间距的小孔通孔和通孔相关的问题。 这是通过将栅极堆叠上的电介质抛光到存在于栅极堆叠上的抛光停止来实现的，以使得具有与栅极堆叠上的抛光停止层的顶表面共面的顶表面。 这建立了在晶片上方的衬底上高度非常均匀的顶表面。 因此，在该顶表面上形成的随后的电介质在晶片上的高度也是非常均匀的。 基于期望保持用于蚀刻的图案通过非常均匀的厚度的层，光致抗蚀剂厚度然后可以被选择为所需的最小厚度。

公开(公告)号：US06884727B2

公开(公告)日：2005-04-26

申请号：US10224675

申请日：2002-08-21

申请人： Da Zhang ,  Terry G. Sparks

发明人： Da Zhang ,  Terry G. Sparks

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/311

CPC分类号： H01L21/0337 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/32139

摘要： A method for forming a sacrificial layer (30) over patterned structures (28) to allow structures (28) to be trimmed laterally without incurring much loss vertically. Structures (28) are patterned on a first layer (26) of a substrate (24). Thereafter, sacrificial layer (30) is deposited on structures (28). During this deposition, the thickness of sacrificial layer (28) grows vertically above structures (28) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer (30) and patterned structures (28) are then etched where the etch rate uniformity ensures that the sacrificial layer (30) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.

摘要翻译： 一种用于在图案化结构（28）上形成牺牲层（30）的方法，以允许结构（28）被横向修剪，而不会垂直引起大量损失。 在衬底（24）的第一层（26）上构图（28）。 此后，牺牲层（30）沉积在结构（28）上。 在该沉积期间，牺牲层（28）的厚度比在其结构侧壁附近生长更快地在结构（28）上方垂直地生长。 然后蚀刻牺牲层（30）和图案化结构（28），其中蚀刻速率均匀性确保覆盖侧壁的牺牲层（30）在覆盖水平部分的牺牲层之前被清除，从而能够蚀刻图案化结构侧壁而不减少 图案结构高度。 牺牲层可以包括用低能量碳氟化合物等离子体形成的聚合物，而随后的蚀刻可以使用氧等离子体。

公开(公告)号：US07741218B2

公开(公告)日：2010-06-22

申请号：US11679512

申请日：2007-02-27

申请人： Terry G. Sparks ,  Robert E. Jones

发明人： Terry G. Sparks ,  Robert E. Jones

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L21/2885 ,  H01L21/76879 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material.

摘要翻译： 讨论了一种用于形成导电通孔的方法，包括在半导体衬底的第一侧上形成晶种层，其中半导体衬底包括与第二侧相对的第一侧，从半导体衬底的第二侧形成通孔 所述半导体衬底，其中所述通孔暴露所述种子层; 以及从所述种子层电镀所述通孔中的导电通孔材料。 在一个实施例中，在种子层上方形成连续的导电层，并电耦合到晶种层。 连续导电层可用作电流源，同时电镀导电通孔材料。

公开(公告)号：US20080206984A1

公开(公告)日：2008-08-28

申请号：US11679512

申请日：2007-02-27

申请人： Terry G. Sparks ,  Robert E. Jones

发明人： Terry G. Sparks ,  Robert E. Jones

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/2885 ,  H01L21/76879 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material.

摘要翻译： 讨论了一种用于形成导电通孔的方法，包括在半导体衬底的第一侧上形成晶种层，其中半导体衬底包括与第二侧相对的第一侧，从半导体衬底的第二侧形成通孔 所述半导体衬底，其中所述通孔暴露所述种子层; 以及从所述种子层电镀所述通孔中的导电通孔材料。 在一个实施例中，在种子层上方形成连续的导电层，并电耦合到晶种层。 连续导电层可用作电流源，同时电镀导电通孔材料。

公开(公告)号：US06686633B1

公开(公告)日：2004-02-03

申请号：US09653338

申请日：2000-08-31

申请人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

发明人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

摘要翻译： 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

公开(公告)号：US06184073B2

公开(公告)日：2001-02-06

申请号：US08997714

申请日：1997-12-23

申请人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

发明人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

摘要翻译： 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。