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11.发明授权公开(公告)号：US09811476B2
公开(公告)日：2017-11-07
申请号：US14769615
申请日：2014-02-06
Inventor： Takuji Maeda , Shinji Inoue , Yoshikazu Katoh
CPC classification number: G06F12/1408 , G06F12/0238 , G06F21/62 , G06F2212/1052 , G06F2212/202 , H04L9/088 , H04L9/0897 , H04L9/14 , H04L2209/605
Abstract: An encryption and recording apparatus storing data, the apparatus including: a first nonvolatile memory; a second nonvolatile memory; and an encryption and decryption control unit, wherein the encryption and decryption control unit: manages an area included in the second nonvolatile memory on a per-block basis, and manages association between a block and a block-unique key using key management information stored in the first nonvolatile memory; receives the data and corresponding information associated with the data; encrypts the data, using one or more block-unique keys associated with one or more blocks included in the second nonvolatile memory and writes the data to the one or more blocks; and stores the corresponding information into the key management information, associating the corresponding information and the one or more block-unique keys.
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公开(公告)号：US09548113B2
公开(公告)日：2017-01-17
申请号：US14938744
申请日：2015-11-11
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C13/004 , G09C1/00 , G11C13/0007 , G11C13/0059 , G11C13/0069 , G11C16/20 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , H04L2209/12
Abstract: A non-volatile memory device includes a memory cell array including memory cells, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a data adjustment circuit. In operation, the read circuit assigns, based on the binary reference value, 0 or 1 to each of the pieces of resistance value information. In operation, the data adjustment circuit determines whether to adjust the binary reference value, in accordance with a difference between the numbers of pieces of digital data “0” and digital data “1” in the pieces of digital data.
Abstract translation: 一种非易失性存储器件包括：存储单元阵列，包括存储单元;读取电路，其工作中获得与每个存储单元之一的电阻值相关的电阻值信息;运算电路， 基于电阻值信息的至少一部分计算二进制参考值和数据调整电路。 在操作中，读取电路基于二进制参考值将0或1分配给每个电阻值信息。 在操作中，数据调整电路根据数字数据中的数字数据“0”和数字数据“1”之间的差异来确定是否调整二进制参考值。
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公开(公告)号：US09390791B2
公开(公告)日：2016-07-12
申请号：US14726636
申请日：2015-06-01
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh , Satoru Ogasahara
IPC: G11C13/00
CPC classification number: G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0076 , G11C2013/0083 , G11C2013/009
Abstract: A data recording method includes recording data in memory cells on the basis of whether each memory cell is in an initial state or a variable state. The recording step includes (A) applying a forming stress to a selected memory cell in the initial state, and (B) setting a resistance value of the selected memory cell to within a first resistance range by (b1) applying a first correction signal to the selected memory cell if the resistance value of the selected memory cell is greater than a first reference value, and (b2) applying a second correction signal to the selected memory cell if the resistance value of the selected memory cell is smaller than a second reference value.
Abstract translation: 数据记录方法包括：根据每个存储单元是处于初始状态还是可变状态，将数据记录在存储器单元中。 记录步骤包括：（A）在初始状态下对所选择的存储单元施加成形应力，（B）通过（b1）将所选存储单元的电阻值设置在第一电阻范围内，将第一校正信号施加到 如果所选择的存储单元的电阻值大于第一参考值，则选择的存储单元，以及（b2）如果所选存储单元的电阻值小于第二参考值，则向所选存储单元施加第二校正信号 值。
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公开(公告)号：US09898598B2
公开(公告)日：2018-02-20
申请号：US14684883
申请日：2015-04-13
Inventor： Yoshikazu Katoh
CPC classification number: G06F21/44 , G09C1/00 , G11C7/1006 , G11C11/005 , G11C13/0007 , G11C13/0059 , G11C13/0069 , G11C2013/0083 , H04L9/32 , H04L9/3278 , H04L2209/12
Abstract: An authentication system comprises a host computer; and a non-volatile memory that includes a memory cell array including a plurality of memory cells are arranged in array, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied; and a memory cell in an initial state which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including first authentication data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state, wherein at least one of the host computer and the non-volatile memory stores second authentication data, and wherein at least one of the host computer and the non-volatile memory is operative to perform authentication on the basis of the first authentication data and the second authentication data.
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公开(公告)号：US09823899B2
公开(公告)日：2017-11-21
申请号：US15180315
申请日：2016-06-13
Inventor： Yoshikazu Katoh
CPC classification number: G06F7/588 , G11C13/0007 , G11C13/004 , G11C13/0059 , G11C2013/0054 , G11C2213/79 , H01L45/146 , H04L9/0869 , H04L9/0894 , H04L9/14 , H04L9/302
Abstract: A random number processing device according to an aspect of the present disclosure is a random number processing device generating random number data by using data read from memory cells, the memory cells having a property such that, in a variable state, in response to application of different electrical signals, a resistance value of each of the memory cells reversibly transitions between resistance value ranges and, when the resistance value falls within at least one resistance value range among the resistance value ranges, the resistance value changes as time passes, the random number processing device including a random number processing circuit that, in operation, generates first random number data from a combination of first resistance value information and second resistance value information about the resistance values of first and second memory cells among the memory cells which fall within the at least one resistance value range.
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Patent Agency Ranking
公开(公告)号：US09536581B2
公开(公告)日：2017-01-03
申请号：US14938022
申请日：2015-11-11
Inventor： Yoshikazu Katoh , Yuhei Yoshimoto , Satoru Ogasahara
IPC: G11C13/00 , G11C7/24 , G06F21/72 , G06F12/14 , G11C29/52 , G06F11/10 , H04L9/32 , G09C1/00 , H04L9/08
CPC classification number: G11C7/24 , G06F11/1072 , G06F12/1408 , G06F21/72 , G06F2212/1052 , G09C1/00 , G11C13/004 , G11C13/0059 , G11C29/52 , H04L9/0866 , H04L9/32 , H04L9/3278 , H04L2209/12
Abstract: A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges in a variable state in accordance with application of different electrical signals, a control circuit that, in operation, receives a control signal, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells in accordance with the control signal, and an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information.
Abstract translation: 非易失性存储器件包括存储单元阵列，其包括存储器单元，每个存储器单元具有根据不同电信号的应用在可变状态的电阻值范围内可逆地转换的电阻值;控制电路，其在操作中接收控制 信号，读取电路，其在操作中根据控制信号获得与存储单元之一的电阻值相关的电阻值信息;以及运算电路，其在运算中基于二进制参考值计算 至少部分电阻值信息。 在操作中，读取电路基于二进制参考值选择性地分配两个值中的一个到每个电阻值信息。
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公开(公告)号：US09053787B2
公开(公告)日：2015-06-09
申请号：US14119936
申请日：2013-03-27
Inventor： Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Akifumi Kawahara
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2013/0083 , G11C2213/15
Abstract: The nonvolatile memory device includes a control circuit that controls a sense amplification circuit and a writing circuit. The control circuit changes a value of at least one of (a) a load current and (b) a forming pulse current or a forming pulse voltage, according to a total number of sneak current paths formed by memory cells each including a variable resistance element in a second resistance state having a low resistance value except a selected memory cell in a memory cell array.
Abstract translation: 非易失性存储器件包括控制读出放大电路和写入电路的控制电路。 控制电路根据由存储单元形成的每个包含可变电阻元件的总体潜流电流路径的总数，改变（a）负载电流和（b）形成脉冲电流或形成脉冲电压中的至少一个的值 在除了存储单元阵列中的所选存储单元之外具有低电阻值的第二电阻状态。
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18.发明授权公开(公告)号：US10410719B2
公开(公告)日：2019-09-10
申请号：US14678571
申请日：2015-04-03
Inventor： Yoshikazu Katoh
Abstract: A non-volatile memory device comprises a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.
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公开(公告)号：US09892783B2
公开(公告)日：2018-02-13
申请号：US15593333
申请日：2017-05-12
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C13/004 , G06F3/0604 , G06F3/0661 , G06F3/0679 , G11C7/24 , G11C13/0007 , G11C13/0059 , G11C13/0061 , G11C13/0069 , G11C2013/0054 , G11C2213/79
Abstract: A non-volatile memory device comprises: a memory cell array that includes one or more memory groups each including memory cells, each of the memory cells having variable resistance value to hold a piece of data; a read circuit that, for each of the one or more memory groups, performs a read operation to obtain pieces of time information related to the memory cells in the memory group; and a data generation circuit that generates individual identification information on a basis of order of the memory cells in each of the one or more memory groups, the order corresponding to ascending order or descending order of the pieces of time information related to the memory cells in the memory group. The read circuit obtains each of the pieces of time information on a basis of a discharge phenomenon or charge phenomenon that depends on the resistance value of a corresponding one of the memory cells.
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公开(公告)号：US09653161B2
公开(公告)日：2017-05-16
申请号：US14938755
申请日：2015-11-11
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0059 , G11C13/0069 , G11C16/20 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083
Abstract: A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.
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