-
公开(公告)号：US10096359B2
公开(公告)日：2018-10-09
申请号：US15594927
申请日：2017-05-15
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
Abstract: A nonvolatile memory device includes: resistive memory cells each of which takes either a variable state or an initial state, the resistive memory cells including at least one resistive memory cell in the initial state; and a read circuit that includes a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell, and a data generation circuit that generates digital data corresponding to the resistance value information. The resistance detection circuit applies a second read voltage to the at least one resistive memory cell to obtain the resistance value information. The second read voltage is larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state. The first read voltage is for reading a resistive memory cell in the variable state.
-
公开(公告)号：US09536581B2
公开(公告)日：2017-01-03
申请号：US14938022
申请日：2015-11-11
Inventor： Yoshikazu Katoh , Yuhei Yoshimoto , Satoru Ogasahara
IPC: G11C13/00 , G11C7/24 , G06F21/72 , G06F12/14 , G11C29/52 , G06F11/10 , H04L9/32 , G09C1/00 , H04L9/08
CPC classification number: G11C7/24 , G06F11/1072 , G06F12/1408 , G06F21/72 , G06F2212/1052 , G09C1/00 , G11C13/004 , G11C13/0059 , G11C29/52 , H04L9/0866 , H04L9/32 , H04L9/3278 , H04L2209/12
Abstract: A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges in a variable state in accordance with application of different electrical signals, a control circuit that, in operation, receives a control signal, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells in accordance with the control signal, and an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information.
Abstract translation: 非易失性存储器件包括存储单元阵列，其包括存储器单元，每个存储器单元具有根据不同电信号的应用在可变状态的电阻值范围内可逆地转换的电阻值;控制电路，其在操作中接收控制 信号，读取电路，其在操作中根据控制信号获得与存储单元之一的电阻值相关的电阻值信息;以及运算电路，其在运算中基于二进制参考值计算 至少部分电阻值信息。 在操作中，读取电路基于二进制参考值选择性地分配两个值中的一个到每个电阻值信息。
-
公开(公告)号：US09640238B2
公开(公告)日：2017-05-02
申请号：US14711785
申请日：2015-05-14
Inventor： Satoru Ogasahara , Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/0035 , G11C13/004 , G11C29/06 , G11C29/36 , G11C2013/0054 , G11C2211/5644
Abstract: A data generating device includes: a memory cell array including a plurality of memory cells; a read circuit operative to obtain a plurality of resistance value information pieces from the plurality of memory cells; and a data generator circuit operative to set a condition on the basis of the plurality of resistance value information pieces, and generating data by allocating, on the basis of the condition, the plurality of resistance value information pieces into a plurality of sets which respectively correspond to a plurality of values constituting the data. Each of the plurality of memory cells has a characteristic where, when in a variable state, a resistance value thereof reversibly changes between a plurality of variable resistance value ranges in accordance with an electric stress applied.
-
Patent Agency Ranking
4.发明授权公开(公告)号：US09484090B2
公开(公告)日：2016-11-01
申请号：US14635297
申请日：2015-03-02
Inventor： Yuhei Yoshimoto , Kazuhiko Shimakawa , Ken Kawai , Ryotaro Azuma
CPC classification number: G11C13/004 , G11C7/062 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C13/0069 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/70 , G11C2013/005 , G11C2013/0054 , G11C2013/0073 , G11C2013/009 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146
Abstract: A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the selected memory cell are provided. In memory cells of odd-numbered-layer and even-numbered-layer memory cell arrays that constitute a multilayer memory cell array, each memory cell in any of the layers has a selection element, a first electrode, a first resistance change layer, a second resistance change layer, and a second electrode that are disposed in the same order. Whether the selected memory cell is located in any layer of the multilayer memory cell array, the read circuit applies a voltage to the selected memory cell to perform the reading operation. The voltage applied to the selected memory cell causes the second electrode to become positive with reference to the first electrode in the selected memory cell.
Abstract translation: 提供从存储单元阵列选择存储单元的选择电路和用于读取所选存储单元中的电阻变化元件的电阻状态的读取电路。 在构成多层存储单元阵列的奇数层和偶数层存储单元阵列的存储单元中，任何层中的每个存储单元都具有选择元件，第一电极，第一电阻改变层， 第二电阻变化层和第二电极。 所选择的存储单元是否位于多层存储单元阵列的任何层中，读取电路向所选存储单元施加电压以执行读取操作。 施加到所选择的存储单元的电压使得第二电极参照所选择的存储单元中的第一电极变为正。
-
公开(公告)号：US09548113B2
公开(公告)日：2017-01-17
申请号：US14938744
申请日：2015-11-11
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C13/004 , G09C1/00 , G11C13/0007 , G11C13/0059 , G11C13/0069 , G11C16/20 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , H04L2209/12
Abstract: A non-volatile memory device includes a memory cell array including memory cells, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a data adjustment circuit. In operation, the read circuit assigns, based on the binary reference value, 0 or 1 to each of the pieces of resistance value information. In operation, the data adjustment circuit determines whether to adjust the binary reference value, in accordance with a difference between the numbers of pieces of digital data “0” and digital data “1” in the pieces of digital data.
Abstract translation: 一种非易失性存储器件包括：存储单元阵列，包括存储单元;读取电路，其工作中获得与每个存储单元之一的电阻值相关的电阻值信息;运算电路， 基于电阻值信息的至少一部分计算二进制参考值和数据调整电路。 在操作中，读取电路基于二进制参考值将0或1分配给每个电阻值信息。 在操作中，数据调整电路根据数字数据中的数字数据“0”和数字数据“1”之间的差异来确定是否调整二进制参考值。
-
公开(公告)号：US09390791B2
公开(公告)日：2016-07-12
申请号：US14726636
申请日：2015-06-01
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh , Satoru Ogasahara
IPC: G11C13/00
CPC classification number: G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0076 , G11C2013/0083 , G11C2013/009
Abstract: A data recording method includes recording data in memory cells on the basis of whether each memory cell is in an initial state or a variable state. The recording step includes (A) applying a forming stress to a selected memory cell in the initial state, and (B) setting a resistance value of the selected memory cell to within a first resistance range by (b1) applying a first correction signal to the selected memory cell if the resistance value of the selected memory cell is greater than a first reference value, and (b2) applying a second correction signal to the selected memory cell if the resistance value of the selected memory cell is smaller than a second reference value.
Abstract translation: 数据记录方法包括：根据每个存储单元是处于初始状态还是可变状态，将数据记录在存储器单元中。 记录步骤包括：（A）在初始状态下对所选择的存储单元施加成形应力，（B）通过（b1）将所选存储单元的电阻值设置在第一电阻范围内，将第一校正信号施加到 如果所选择的存储单元的电阻值大于第一参考值，则选择的存储单元，以及（b2）如果所选存储单元的电阻值小于第二参考值，则向所选存储单元施加第二校正信号 值。
-
公开(公告)号：US09892783B2
公开(公告)日：2018-02-13
申请号：US15593333
申请日：2017-05-12
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C13/004 , G06F3/0604 , G06F3/0661 , G06F3/0679 , G11C7/24 , G11C13/0007 , G11C13/0059 , G11C13/0061 , G11C13/0069 , G11C2013/0054 , G11C2213/79
Abstract: A non-volatile memory device comprises: a memory cell array that includes one or more memory groups each including memory cells, each of the memory cells having variable resistance value to hold a piece of data; a read circuit that, for each of the one or more memory groups, performs a read operation to obtain pieces of time information related to the memory cells in the memory group; and a data generation circuit that generates individual identification information on a basis of order of the memory cells in each of the one or more memory groups, the order corresponding to ascending order or descending order of the pieces of time information related to the memory cells in the memory group. The read circuit obtains each of the pieces of time information on a basis of a discharge phenomenon or charge phenomenon that depends on the resistance value of a corresponding one of the memory cells.
-
公开(公告)号：US09653161B2
公开(公告)日：2017-05-16
申请号：US14938755
申请日：2015-11-11
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0059 , G11C13/0069 , G11C16/20 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083
Abstract: A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.018 seconds)
