公开(公告)号：US06943592B2

公开(公告)日：2005-09-13

申请号：US10858231

申请日：2004-06-01

Applicant: Hubert Degoirat ,  Mathieu Lisart

Inventor： Hubert Degoirat ,  Mathieu Lisart

IPC: G01R19/165 ,  H03K5/153

CPC classification number: G01R19/1659 ,  G01R19/16519

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract translation: 本公开涉及集成电路中电源电压电平的检测器。 所公开的检测器被设计为检测低电平电平的交叉。 它包括第一臂以限定第一参考电压和第二臂以限定第二参考电压，这两个参考电压作为电源电压的函数而变化，并且它们的变化曲线与位于关闭处的电源电压的值相交 达到期望的阈值。 比较器接收两个参考电压。 第一臂具有电阻分压器桥，其中间连接器构成第一参考电压。 第二臂包括与天然P型MOS晶体管串联连接的电阻器，该电阻器的该结点与该晶体管构成第二参考电压。 非线性元件可以并联连接到构成第一参考电压的电阻器。

公开(公告)号：US6151245A

公开(公告)日：2000-11-21

申请号：US215650

申请日：1998-12-17

Applicant: Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

Inventor： Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC classification number: H01L27/115 ,  H01L27/02

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract translation: EEPROM单元被描述为具有在第一金属层中优选形成的屏蔽金属结构，并且在浮动栅极端子处基本上覆盖关系。 这样可以通过测量浮栅端子上的电荷量来获得异常读数的可能性。 可以提供要在第三和随后的金属层中形成的另外的筛选金属结构，以完全覆盖电池并提供额外的防止异常读数的保护。

公开(公告)号：US5384749A

公开(公告)日：1995-01-24

申请号：US96687

申请日：1993-07-23

Applicant: Mathieu Lisart ,  Laurent Sourgen

Inventor： Mathieu Lisart ,  Laurent Sourgen

IPC: G06F3/08 ,  G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F21/02 ,  G06K19/073 ,  G07F7/10 ,  G11C7/24 ,  G11C8/04 ,  G11C16/02 ,  G11C17/00 ,  G11C11/40

CPC classification number: G11C8/04 ,  G06F12/1441 ,  G06Q20/341 ,  G06Q20/35765 ,  G07F7/1008 ,  G11C7/24

Abstract: In a memory, a zone descriptor contains authorizations to act which may pertain to actions of reading, writing and erasure and which concerns memory words of a zone of the memory controlled by this descriptor. The zone descriptor also has an information element indicating the length of the memory zone by including the address of the next descriptor. An internal zone control signal is produced in order to store a mode of management of the memory zone and, an address corresponding to the end of the zone. The end of zone address is then compared with the addresses delivered by an address counter. A modification of the stored information is prompted when the end of a zone is reached.

Abstract translation: 在存储器中，区域描述符包含作用的授权，其可以涉及读取，写入和擦除的动作，并且涉及由该描述符控制的存储器区域的存储器字。 区域描述符还具有通过包括下一描述符的地址来指示存储区的长度的信息元素。 产生内部区域控制信号，以便存储存储器区域的管理模式以及对应于该区域的结尾的地址。 然后将区域地址的结束与由地址计数器传递的地址进行比较。 当到达区域的末尾时，将提示存储的信息的修改。

公开(公告)号：US20120320477A1

公开(公告)日：2012-12-20

申请号：US13523599

申请日：2012-06-14

Applicant: Mathieu Lisart ,  Alexandre Sarafianos

Inventor： Mathieu Lisart ,  Alexandre Sarafianos

IPC: H02H3/46 ,  H01L21/8238 ,  H02H7/00 ,  H01L23/58

CPC classification number: H01L23/576 ,  H01L21/763 ,  H01L23/585 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip.

Abstract translation: 一种集成电路芯片，包括形成在第一导电类型的半导体衬底的上部的多个交替导电类型的平行阱，以及防止攻击的装置，包括：阱之间，具有填充有导电的绝缘壁的沟槽 材料，所述沟槽从孔的上表面延伸到衬底; 以及能够检测在所述导电材料和芯片的区域之间形成的杂散电容的修改的电路。

公开(公告)号：USRE42144E1

公开(公告)日：2011-02-15

申请号：US12512940

申请日：2009-07-30

Applicant: Mathieu Lisart

Inventor： Mathieu Lisart

IPC: G11C11/00

CPC classification number: G11C16/26 ,  G11C16/22

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

Abstract translation: 非易失性存储器技术领域本发明涉及一种非易失性存储器，其包括存储器阵列，该存储器阵列包括与至少一个非功能字线连接的功能存储单元和非功能存储单元 字线地址解码器包括链接到非功能字线的特殊解码部分，用于当功能字线被读取选择时选择非功能字线，使得与功能性字符串同时选择非功能性存储器单元 存储单元，并扭曲功能存储单元的读数。 特别适用于智能卡集成电路。

公开(公告)号：US20100318885A1

公开(公告)日：2010-12-16

申请号：US12815684

申请日：2010-06-15

Applicant: Mathieu Lisart ,  Julien Mercier

Inventor： Mathieu Lisart ,  Julien Mercier

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/1032 ,  G11C7/24

Abstract: A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.

Abstract translation: 存储器设备可以包括存储器平面，其包括被配置为存储包括数据位和奇偶校验位的位块的存储器单元组，以及用于检测包括读取器读取每个位的故障注入的检测器，以及执行第一检查器 当读取块时，基于每个数据和奇偶校验位的读取值进行奇偶校验。 存储器平面可以包括布置在一些存储器单元之间的参考存储器单元，以创建m个存储器单元的分组。 当m大于1时，每个参考存储单元可以存储参考位，并且m个存储器单元的每个分组可存储相关块的m位，具有不同的奇偶校验。 检测器还可以包括第二检查器，以在读取块时执行对每个参考位的值的检查。

公开(公告)号：US07251151B2

公开(公告)日：2007-07-31

申请号：US11106048

申请日：2005-04-14

Applicant: Mathieu Lisart

Inventor： Mathieu Lisart

IPC: G11C11/00

CPC classification number: G11C16/26 ,  G11C16/22

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

Abstract translation: 非易失性存储器技术领域本发明涉及一种非易失性存储器，其包括存储器阵列，该存储器阵列包括与至少一个非功能字线连接的功能存储器单元和非功能存储器单元。 字线地址解码器包括链接到非功能字线的特殊解码部分，用于当功能字线被读取选择时选择非功能字线，使得与功能性字符串同时选择非功能性存储器单元 存储单元，并扭曲功能存储单元的读数。 特别适用于智能卡集成电路。

公开(公告)号：US20070033380A1

公开(公告)日：2007-02-08

申请号：US11493865

申请日：2006-07-25

Applicant: Mathieu Lisart ,  Nicolas Demange

Inventor： Mathieu Lisart ,  Nicolas Demange

IPC: G06F15/00

CPC classification number: G06F21/556 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/24

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract translation: 一种方法使用根据用于将电信号分配给处理电路的规则处理电信号的连续循环的并行处理电路来处理并行电信号。 该方法包括在处理周期之间，修改用于将电信号分配给处理电路的规则的步骤，使得处理电路在不同处理周期期间处理不同等级的电信号。 该方法可以特别用于在存储器的读取阶段和使用这种存储器的微处理器的集成电路中保护存储器。

公开(公告)号：US20050232021A1

公开(公告)日：2005-10-20

申请号：US11106048

申请日：2005-04-14

Applicant: Mathieu Lisart

Inventor： Mathieu Lisart

IPC: G11C7/24 ,  G11C16/22 ,  G11C16/26 ,  G11C17/00

CPC classification number: G11C16/26 ,  G11C16/22

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

Abstract translation: 非易失性存储器技术领域本发明涉及一种非易失性存储器，其包括存储器阵列，该存储器阵列包括与至少一个非功能字线连接的功能存储器单元和非功能存储器单元。 字线地址解码器包括链接到非功能字线的特殊解码部分，用于当功能字线被读取选择时选择非功能字线，使得与功能性字符串同时选择非功能性存储器单元 存储单元，并扭曲功能存储单元的读数。 特别适用于智能卡集成电路。

公开(公告)号：US08946859B2

公开(公告)日：2015-02-03

申请号：US13523599

申请日：2012-06-14

Applicant: Mathieu Lisart ,  Alexandre Sarafianos

Inventor： Mathieu Lisart ,  Alexandre Sarafianos

IPC: H01L21/70 ,  H01L23/00 ,  H01L21/763 ,  H01L23/58 ,  H01L27/092

CPC classification number: H01L23/576 ,  H01L21/763 ,  H01L23/585 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip.

Abstract translation: 一种集成电路芯片，包括形成在第一导电类型的半导体衬底的上部的多个交替导电类型的平行阱，以及防止攻击的装置，包括：阱之间，具有填充有导电的绝缘壁的沟槽 材料，所述沟槽从孔的上表面延伸到衬底; 以及能够检测在所述导电材料和芯片的区域之间形成的杂散电容的修改的电路。