公开(公告)号：US07388802B2

公开(公告)日：2008-06-17

申请号：US11423852

申请日：2006-06-13

Applicant: Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

Inventor： Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

IPC: G11C8/00 ,  G11C5/06 ,  G11C7/00 ,  G11C8/02 ,  G06F12/00

CPC classification number: G11C8/20 ,  G11C7/24 ,  G11C16/22

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract translation: 存储器包括布置在存储器阵列中的存储单元，以及地址解码器，用于根据应用于存储器的读取地址将存储单元选择信号应用于存储器阵列。 存储器包括地址重构电路，其从存储器单元选择信号重建读取地址的至少一部分，并且提供能够检测影响选择信号的错误注入的第一重建地址。 特别但不排他地适用于芯片卡的集成电路。

公开(公告)号：US5889720A

公开(公告)日：1999-03-30

申请号：US852104

申请日：1997-05-06

Applicant: Mathieu Lisart ,  Laurent Sourgen

Inventor： Mathieu Lisart ,  Laurent Sourgen

IPC: G11C16/12 ,  H03K4/00 ,  G11C13/00

CPC classification number: H03K4/00 ,  G11C16/12

Abstract: To form a ramp signal for the programming of a memory cell without losing excess voltage in a control circuit, the output of a voltage pull-up circuit is connected to the programming input using a P type transistor. It is shown that this P type transistor then charges the memory array at constant current, prompting a linear increase of the voltage. This results in preventing the memory cell that is to be programmed from being subjected to excessively sudden variations of voltage. It is shown that by acting in this way, the integrated circuit can be made to work even with very low voltages.

Abstract translation: 为了形成用于编程存储器单元的斜坡信号，而不会在控制电路中损失过多的电压，使用P型晶体管将电压上拉电路的输出连接到编程输入。 这表明该P型晶体管然后以恒定电流对存储器阵列充电，促使电压线性增加。 这导致防止被编程的存储单元经受过度突然的电压变化。 显示出通过这样的方式，即使在非常低的电压下也可以使集成电路工作。

公开(公告)号：US5500601A

公开(公告)日：1996-03-19

申请号：US839618

申请日：1992-02-21

Applicant: Mathieu Lisart ,  Richard Fournel

Inventor： Mathieu Lisart ,  Richard Fournel

IPC: G01D5/16 ,  G01D5/18 ,  G06F1/00 ,  G06F21/55 ,  G11C16/28 ,  G01R27/08 ,  G01R31/26 ,  G11C29/00

CPC classification number: G06F21/558 ,  G01D5/16 ,  G01D5/18 ,  G11C16/28 ,  G06F2207/7219

Abstract: The invention is a device to detect the logic state of a component whose impedance depends on this state, the device including means to generate a current and a measurement voltage so that the current consumption remains constant during cell detection regardless of the state detected, the device also including means to detect the logic state of the component.

Abstract translation: 本发明是一种用于检测其阻抗取决于该状态的部件的逻辑状态的装置，该装置包括产生电流和测量电压的装置，使得在小区检测期间电流消耗保持恒定，而与检测到的状态无关，该装置 还包括检测组件的逻辑状态的方法。

公开(公告)号：US08532947B2

公开(公告)日：2013-09-10

申请号：US12969266

申请日：2010-12-15

Applicant: Pascal Fornara ,  Mathieu Lisart

Inventor： Pascal Fornara ,  Mathieu Lisart

IPC: G01R19/00 ,  G06F19/00

CPC classification number: G06K19/067 ,  H01L23/48 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/54446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit.

Abstract translation: 集成电路包括被配置为秘密地存储数字字的非易失性存储器，其数值字形成识别码。 集成电路还包括配置成接收数字字并产生瞬态电流或瞬态电压的控制电路，其特性取决于数字字的值。 存在导电网络，其配置为通过电流通过或接收瞬态电压，以便产生识别集成电路的电磁场。

公开(公告)号：US6147521A

公开(公告)日：2000-11-14

申请号：US876282

申请日：1997-06-12

Applicant: Hubert Degoirat ,  Mathieu Lisart

Inventor： Hubert Degoirat ,  Mathieu Lisart

IPC: G01R19/165 ,  H03K5/153 ,  H03K3/037

CPC classification number: G01R19/1659 ,  G01R19/16519

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

公开(公告)号：US5859526A

公开(公告)日：1999-01-12

申请号：US871096

申请日：1997-06-06

Applicant: Tien-Dung Do ,  Mathieu Lisart

Inventor： Tien-Dung Do ,  Mathieu Lisart

IPC: G05F3/24 ,  G11C5/14 ,  G05F1/40

CPC classification number: G11C5/147 ,  G05F3/242

Abstract: A voltage reference generator includes a voltage source and a differential amplifier. The voltage source supplies a stable voltage reference to a positive input of the differential amplifier which is configured as a follower having its output looped back to its negative input. The negative feedback loop is a variable-resistance loop that is controlled by the output of the differential amplifier. The variable-resistance feedback loop transiently imposes open-loop operation when the voltage reference generator is turned on so as to provide high current to the output before imposing closed-loop operation in follower mode.

Abstract translation: 电压基准发生器包括电压源和差分放大器。 电压源为差分放大器的正输入提供稳定的参考电压，差分放大器的正输入被配置为具有循环回到其负输入的引导器。 负反馈回路是由差分放大器的输出控制的可变电阻回路。 当电压基准发生器导通时，可变电阻反馈环路瞬时施加开环操作，以便在跟随器模式下施加闭环操作之前向输出端提供高电流。

公开(公告)号：US09323941B2

公开(公告)日：2016-04-26

申请号：US12942557

申请日：2010-11-09

Applicant: Fabrice Marinet ,  Mathieu Lisart

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G06F11/30 ,  G06F12/14 ,  H04L29/06 ,  G06F21/62 ,  G06F21/78 ,  G06F11/14 ,  G06F21/77

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.

Abstract translation: 该组件包括第一存储器（MM），其包括具有由第一修改实体（K1）修改的内容的第一部分（P1）和具有用第二实体（K2）修改的内容的第二部分（P2），存储装置 （MS）被配置为秘密地存储第一实体（K1），非易失性存储器（NVM）将代表第二实体（K2）的实体信息项存储在由第一指示（INDK2）指定的位置（END）中， 包含在第一存储器的所述第一部分中。

公开(公告)号：US08397152B2

公开(公告)日：2013-03-12

申请号：US12815684

申请日：2010-06-15

Applicant: Mathieu Lisart ,  Julien Mercier

Inventor： Mathieu Lisart ,  Julien Mercier

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/1032 ,  G11C7/24

Abstract: A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.

Abstract translation: 存储器设备可以包括存储器平面，其包括被配置为存储包括数据位和奇偶校验位的位块的存储器单元组，以及用于检测包括读取器读取每个位的故障注入的检测器，以及执行第一检查器 当读取块时，基于每个数据和奇偶校验位的读取值进行奇偶校验。 存储器平面可以包括布置在一些存储器单元之间的参考存储器单元，以创建m个存储器单元的分组。 当m大于1时，每个参考存储单元可以存储参考位，并且m个存储器单元的每个分组可存储相关块的m位，具有不同的奇偶校验。 检测器还可以包括第二检查器，以在读取块时执行对每个参考位的值的检查。

公开(公告)号：US20120320480A1

公开(公告)日：2012-12-20

申请号：US13495945

申请日：2012-06-13

Applicant: Mathieu Lisart ,  Alexandre Sarafianos ,  Olivier Gagliano ,  Marc Mantelli

Inventor： Mathieu Lisart ,  Alexandre Sarafianos ,  Olivier Gagliano ,  Marc Mantelli

IPC: H02H3/44 ,  H01L21/8238

CPC classification number: H01L23/576 ,  H01L21/763 ,  H01L23/585 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer.

Abstract translation: 集成电路芯片包括：形成在第一导电类型的半导体衬底的上部的多个交替导电类型的平行阱; 在第一类型的每个阱中，具有第二导电类型的沟道的多个MOS晶体管，并且在第二类型的每个阱中，具有第一类型的沟道的多个MOS晶体管，相邻阱的晶体管被​​反相 -连接的; 以及防止攻击的装置，包括：从所述井的下表面在所述多个井下延伸的第二类型的层; 以及井之间的侧向绝缘区域，所述区域从孔的上表面延伸到所述层。

公开(公告)号：US06943592B2

公开(公告)日：2005-09-13

申请号：US10858231

申请日：2004-06-01

Applicant: Hubert Degoirat ,  Mathieu Lisart

Inventor： Hubert Degoirat ,  Mathieu Lisart

IPC: G01R19/165 ,  H03K5/153

CPC classification number: G01R19/1659 ,  G01R19/16519

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract translation: 本公开涉及集成电路中电源电压电平的检测器。 所公开的检测器被设计为检测低电平电平的交叉。 它包括第一臂以限定第一参考电压和第二臂以限定第二参考电压，这两个参考电压作为电源电压的函数而变化，并且它们的变化曲线与位于关闭处的电源电压的值相交 达到期望的阈值。 比较器接收两个参考电压。 第一臂具有电阻分压器桥，其中间连接器构成第一参考电压。 第二臂包括与天然P型MOS晶体管串联连接的电阻器，该电阻器的该结点与该晶体管构成第二参考电压。 非线性元件可以并联连接到构成第一参考电压的电阻器。