公开(公告)号：US07655983B2

公开(公告)日：2010-02-02

申请号：US11757472

申请日：2007-06-04

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L31/119 ,  H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

公开(公告)号：US20080296676A1

公开(公告)日：2008-12-04

申请号：US11757472

申请日：2007-06-04

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

公开(公告)号：US06949764B2

公开(公告)日：2005-09-27

申请号：US10993244

申请日：2004-11-19

申请人： Tak Hung Ning

发明人： Tak Hung Ning

IPC分类号： H01L21/8249 ,  H01L21/331 ,  H01L27/12 ,  H01L29/08 ,  H01L29/73 ,  H01L29/40

CPC分类号： H01L29/66265 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/7317

摘要： A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical bipolar transistors on semiconductor material having a thickness of 300 nm or less and to permit the fabrication of SOI BiCMOS. The invention overcomes the problem of requiring a thick semiconductor layer in SOI to fabricate vertical bipolar transistors with low collector resistance.

摘要翻译： 描述了双极晶体管结构，其结合了在绝缘体上硅（SOI）衬底的绝缘体上具有完全耗尽区的发射极，基极和集电极，而不需要高掺杂子集电极以允许制造垂直双极晶体管 半导体材料的厚度为300nm以下，能制造SOI BiCMOS。 本发明克服了在SOI中需要厚的半导体层来制造具有低集电极电阻的垂直双极晶体管的问题。

公开(公告)号：US06870213B2

公开(公告)日：2005-03-22

申请号：US10143291

申请日：2002-05-10

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7881

摘要： A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.

摘要翻译： 公开了一种适用于大规模集成的低编程能力的高速EEPROM器件。 该装置包括主体，源极，漏极，并且具有用于将编程电流注入到体内的装置。 来自身体的热载体进入浮动门，效率高于通道载流子能够做到的效率。 该器件的漏极电流由器件偏置控制。 该装置建立在绝缘体上，底部共同板和顶侧体。 这些特性使得器件成为SOI和薄膜技术的理想选择。

公开(公告)号：US06525427B2

公开(公告)日：2003-02-25

申请号：US10055704

申请日：2002-01-22

申请人： Peter Richard Duncombe ,  Daniel Charles Edelstein ,  Robert Benjamin Laibowitz ,  Deborah Ann Neumayer ,  Tak Hung Ning ,  Robert Rosenberg ,  Thomas Mcarraoll Shaw

发明人： Peter Richard Duncombe ,  Daniel Charles Edelstein ,  Robert Benjamin Laibowitz ,  Deborah Ann Neumayer ,  Tak Hung Ning ,  Robert Rosenberg ,  Thomas Mcarraoll Shaw

IPC分类号： H01L2348

CPC分类号： H01L28/55 ,  H01L21/31691 ,  H01L23/5223 ,  H01L23/5329 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

公开(公告)号：US20110298056A1

公开(公告)日：2011-12-08

申请号：US12793046

申请日：2010-06-03

申请人： Tak Hung Ning ,  Zhen Zhang

发明人： Tak Hung Ning ,  Zhen Zhang

IPC分类号： H01L23/532 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L29/0847 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.

摘要翻译： 在半导体器件中形成低电阻接触结构的方法包括在半导体衬底中形成掺杂半导体区域; 在所述掺杂半导体区域的上部形成深层杂质区域; 通过退火激活掺杂半导体区域和深层杂质区域中的掺杂剂; 以及在深层杂质区上形成金属接触，从而在它们之间产生金属 - 半导体界面。

公开(公告)号：US20100105175A1

公开(公告)日：2010-04-29

申请号：US12651499

申请日：2010-01-04

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

公开(公告)号：US07244976B2

公开(公告)日：2007-07-17

申请号：US11042866

申请日：2005-01-25

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L27/10

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7881

摘要： A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.

摘要翻译： 公开了一种适用于大规模集成的低编程能力的高速EEPROM器件。 该装置包括主体，源极，漏极，并且具有用于将编程电流注入到体内的装置。 来自身体的热载体进入浮动门，效率高于通道载流子能够做到的效率。 该器件的漏极电流由器件偏置控制。 该装置建立在绝缘体上，底部共同板和顶侧体。 这些特性使得器件成为SOI和薄膜技术的理想选择。

公开(公告)号：US5886376A

公开(公告)日：1999-03-23

申请号：US673974

申请日：1996-07-01

申请人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

发明人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/7881

摘要： An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

摘要翻译： 电可擦除可编程只读存储器CEEPROM）包括场效应晶体管和在第一绝缘层上间隔开的控制栅极，形成在场效应晶体管上的第二绝缘层和控制栅极以及第二绝缘层上的公共浮栅 层叠在场效应晶体管和控制栅极的沟道上，因此浮置栅极也形成场效应晶体管的栅电极。 EEPROM器件可以互连在存储器阵列中，并且多个存储器阵列可以堆叠在另一个上。 本发明克服了使用非标准绝缘体上硅（SOI）CMOS工艺来制造具有高面密度的EEPROM阵列的问题。

公开(公告)号：US5017990A

公开(公告)日：1991-05-21

申请号：US445251

申请日：1989-12-01

申请人： Tze-Chiang Chen ,  Ching-Te Kent Chuang ,  Guann-Pyng Li ,  Tak Hung Ning

发明人： Tze-Chiang Chen ,  Ching-Te Kent Chuang ,  Guann-Pyng Li ,  Tak Hung Ning

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/732

摘要： The invention relates to a bipolar transistor structure which includes a layer of semiconductor material having a single crystal raised base, a single crystal or polycrystalline emitter and adjacent polycrystalline regions which provide an electrical connection to the emitter. The invention also relates to the method of fabricating such a structure and includes the step of depositing a conformal layer of semiconductor material of one conductivity type over a region of opposite conductivity and over insulation such that single crystal and polycrystalline regions form over single crystal material and insulation, respectively. In a subsequent step, a layer of opposite conductivity type semiconductor material is deposited on the first layer forming single crystal or polycrystalline material over single crystal and polycrystalline material over polycrystalline. Then, in a final step, the structure is subjected to an out-diffusion step which simultaneously forms a single crystal emitter region of opposite conductivity type, a p-n junction in the one conductivity type single crystal region and regions of opposite conductivity type which act as an interconnection to the emitter region.