-
11.发明授权Imaging cell with a non-volatile memory that provides a long integration period and method of operating the imaging cell 有权具有非易失性存储器的成像单元，其提供长的积分期和操作成像单元的方法公开(公告)号：US06972995B1
公开(公告)日：2005-12-06
申请号：US10821391
申请日：2004-04-09
CPC分类号： G11C27/005 , G11C16/10
摘要： The image capture period of an imaging cell, or the total time that an imaging cell is exposed to light energy, is substantially increased by utilizing a non-volatile memory (NVM), such as an electrically-erasable, programmable, read-only-memory (EEPROM) structure. The NVM structure stores and integrates charges that are proportional to the absorbed photons over a large number of sequential integration periods.
摘要翻译： 成像单元的图像捕获周期或成像单元暴露于光能的总时间通过利用诸如电可擦除可编程的只读存储器之类的非易失性存储器（NVM）而显着增加， 存储器（EEPROM）结构。 NVM结构在大量的顺序集成周期内存储和积分与吸收的光子成比例的电荷。
-
12.发明申请PHOTODIODE THAT INCORPORATES A CHARGE BALANCED SET OF ALTERNATING N AND P DOPED SEMICONDUCTOR REGIONS 审中-公开包含N和P多个半导体区域的充电平衡组的光电公开(公告)号：US20120326260A1
公开(公告)日：2012-12-27
申请号：US13165050
申请日：2011-06-21
CPC分类号： H01L31/103 , H01L31/03529 , Y02E10/50
摘要： A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal.
摘要翻译： 光电二极管包括形成在半导体衬底的表面中的第一端子; 形成在所述基板表面中并与所述第一端子间隔开的第二端子; 以及形成在第一端子和第二端子之间的衬底表面中的多个相邻的交替的N型和P型扩散区域。
-
13.发明授权公开(公告)号：US08324603B2
公开(公告)日：2012-12-04
申请号：US12862136
申请日：2010-08-24
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
摘要： Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
摘要翻译： 方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。 与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。
-
14.发明申请公开(公告)号：US20110174999A1
公开(公告)日：2011-07-21
申请号：US12862136
申请日：2010-08-24
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
摘要： Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
摘要翻译： 方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。 与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。
-
15.发明授权公开(公告)号：US07192857B1
公开(公告)日：2007-03-20
申请号：US11109961
申请日：2005-04-20
IPC分类号： H01L21/3205
CPC分类号： H01L29/41758 , H01L23/4824 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.
摘要翻译： 功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。 电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。
-
公开(公告)号：US06798641B1
公开(公告)日：2004-09-28
申请号：US10647602
申请日：2003-08-25
IPC分类号： H01G4228
CPC分类号： H01L27/0805 , H01L29/92
摘要： A multiple-layer diffusion junction capacitor structure includes multiple layers of inter-digitated P-type dopant and N-type dopant formed in a semiconductor substrate. An opening in a hard mask is formed taking care to control the angle of the sidewall using a dry, anisotropic etching process. P-type and N-type dopant are then implanted at positive and negative shallow angles, respectively, each with a different energy and dose. By utilizing the properly determined implant angles, implant energies and implant doses for each of the dopant types, a high capacitance and high density diode junction capacitor, with inter-digitated N-type and P-type regions in the vertical direction is provided.
摘要翻译： 多层扩散结电容器结构包括在半导体衬底中形成的多层数字化P型掺杂剂和N型掺杂剂。 形成硬掩模的开口，其中形成了使用干燥的各向异性蚀刻工艺来控制侧壁的角度。 然后分别以正和负的浅角度注入P型和N型掺杂剂，每种具有不同的能量和剂量。 通过利用适当确定的植入角度，提供每种掺杂剂类型的注入能量和注入剂量，高电容和高密度二极管结电容器，在垂直方向上具有数字化的N型和P型区域。
-
17.发明授权Method of forming a high-voltage silicon controlled rectifier structure with improved punch through resistance 有权形成具有改善的穿通电阻的高压可控硅整流器结构的方法公开(公告)号：US07238553B1
公开(公告)日：2007-07-03
申请号：US11134911
申请日：2005-05-23
IPC分类号： H01L21/332
CPC分类号： H01L27/0248 , H01L29/7436
摘要： When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.
摘要翻译： 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过形成一个晶体管的发射极，与另一个晶体管的下沉区域的尾部相邻。
-
18.发明授权Vertical photodiode with heavily-doped regions of alternating conductivity types 有权具有交替导电类型的重掺杂区域的垂直光电二极管公开(公告)号：US07105373B1
公开(公告)日：2006-09-12
申请号：US10640963
申请日：2003-08-14
IPC分类号： H01L21/00
CPC分类号： H01L31/028 , H01L31/103 , Y02E10/547
摘要： A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a highly doped sinker of a first conductivity type contacts each first region, and a highly doped sinker of a second conductivity type contacts each second region.
摘要翻译： 单结交叉光电二极管利用第一导电类型的交替的高度掺杂的第一区域和第二导电类型的高度掺杂的第二区域的堆叠，其在下面形成并接触第一区域以收集光子。 此外，第一导电类型的高掺杂沉降片接触每个第一区域，并且第二导电类型的高掺杂沉降片接触每个第二区域。
-
公开(公告)号：US07050314B1
公开(公告)日：2006-05-23
申请号：US10625961
申请日：2003-07-23
IPC分类号： H02M3/18
CPC分类号： H02M3/07
摘要： A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.
摘要翻译： 一种电荷泵电路，其中至少一个开关元件采取LVTSCR的形式。 LVTSCR的接通和断开可以通过使用脉冲输入并依靠LVTSCR的触发和保持电压来接通和关断来实现。
-
20.发明授权High-voltage silicon controlled rectifier structure with improved punch through resistance 有权高压可控硅整流器结构，具有改善的穿通电阻公开(公告)号：US06919588B1
公开(公告)日：2005-07-19
申请号：US10650000
申请日：2003-08-27
CPC分类号： H01L27/0248 , H01L29/7436
摘要： When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.
摘要翻译： 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过形成一个晶体管的发射极，与另一个晶体管的下沉区域的尾部相邻。
-
-
-
-
-
-
-
-
-
搜索结果
68 条记录 (耗时 0.021 秒)
