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282 条记录 (耗时 0.038 秒)

    Dual direction ESD clamp based on snapback NMOS cell with embedded SCR
    3.
    发明授权
    Dual direction ESD clamp based on snapback NMOS cell with embedded SCR 有权
    基于具有嵌入式SCR的快速恢复NMOS单元的双向ESD钳位

    公开(公告)号：US07394133B1

    公开(公告)日：2008-07-01

    申请号：US11216774

    申请日：2005-08-31

    申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

    发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

    IPC分类号： H01L29/72

    CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/87

    摘要： In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.

    摘要翻译： 在ESD保护结构中，通过在NMOS器件周围形成n阱隔离环来提供双向ESD保护，使得形成NMOS漏极的p阱通过n阱与下面的p衬底隔离 隔离环。 通过形成n阱隔离环，提供了用于反向ESD保护的嵌入式SCR的p-n-p-n结构。 调整n阱隔离环的宽度及其与NMOS漏极的间隔，以提供所需的SCR参数。

    Imaging cell that has a long integration period and method of operating the imaging cell
    4.
    发明授权
    Imaging cell that has a long integration period and method of operating the imaging cell 有权
    成像细胞具有长的积分期和操作成像细胞的方法

    公开(公告)号：US07218555B2

    公开(公告)日：2007-05-15

    申请号：US11242094

    申请日：2005-10-03

    申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

    发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

    IPC分类号： G11C11/34 ,  H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/14603 ,  H01L27/14609

    摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

    摘要翻译： 成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。 光能从EPROM结构的沟道区形成光电子。 光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。

    NVM PMOS-cell with one erased and two programmed states
    6.
    发明授权
    NVM PMOS-cell with one erased and two programmed states 有权
    NVM PMOS单元具有一个擦除和两个编程状态

    公开(公告)号：US07113427B1

    公开(公告)日：2006-09-26

    申请号：US11076711

    申请日：2005-03-09

    申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

    发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7881

    摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.

    摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。

    High-speed photon detector and method of forming the detector
    7.
    发明授权
    High-speed photon detector and method of forming the detector 有权
    高速光子探测器及形成探测器的方法

    公开(公告)号：US07057174B1

    公开(公告)日：2006-06-06

    申请号：US10355904

    申请日：2003-01-30

    申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Michael Mian

    发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Michael Mian

    IPC分类号： H01L31/00

    CPC分类号： H01L31/08

    摘要： A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed adjacent to the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in the magnetic flux.

    摘要翻译： 能够检测千兆赫兹光信号的光子检测器利用与电感线圈相邻形成的光子材料层。 当脉冲光源被施加到光子材料层时，光子材料产生改变电感器的磁通量的涡流。 然后可以通过检测磁通量的变化来检测信号。

    Self-protecting transistor array
    9.
    发明授权
    Self-protecting transistor array 有权
    自保护晶体管阵列

    公开(公告)号：US07217966B1

    公开(公告)日：2007-05-15

    申请号：US11060877

    申请日：2005-02-18

    申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

    发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

    IPC分类号： H01L27/10 ,  H01L29/739 ,  H01L29/73 ,  H01L29/74

    CPC分类号： H01L27/0266 ,  H01L29/78

    摘要： A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.

    摘要翻译： 晶体管阵列可以通过将ESD保护器件集成到晶体管阵列中而免受静电放电（ESD）事件的影响，从而导致局部ESD损坏。 ESD保护装置在正常操作条件下作为晶体管工作，并且在ESD事件期间提供低电阻电流路径。

    Ultra low leakage MOSFET transistor
    10.
    发明授权
    Ultra low leakage MOSFET transistor 有权
    超低漏电MOSFET晶体管

    公开(公告)号：US07202538B1

    公开(公告)日：2007-04-10

    申请号：US10647604

    申请日：2003-08-25

    申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

    发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

    IPC分类号： H01L29/94

    CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0692

    摘要： A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region. Thus, an enclosed ring is maintained around the entire composite perimeter, thereby completely avoiding regions of high trap density and, thus, preventing any current path for gate induced drain leakage (GIDL) to occur.

    摘要翻译： 在具有第一导电类型的半导体材料的衬底中形成MOSFET晶体管结构。 MOSFET晶体管结构包括由形成在衬底中的周边隔离电介质材料围绕以限定侧壁电介质材料和有源区域之间的连续侧壁界面的有源区域。 间隔开的源极和漏极区域形成在有源区中并且也与侧壁界面间隔开。 通过介入栅极电介质材料与衬底沟道区分离的导电栅电极包括在衬底沟道区上延伸的第一部分和在隔离电介质材料与有源区之间的整个侧壁界面上连续延伸的第二部分。 因此，围绕整个复合材料周边保持封闭的环，从而完全避免高陷阱密度的区域，并因此防止发生栅极引起漏极泄漏（GIDL）的任何电流路径。