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    APPARATUS AND METHOD FOR IMPROVED LOCK ELISION TECHNIQUES
    11.
    发明申请
    APPARATUS AND METHOD FOR IMPROVED LOCK ELISION TECHNIQUES 有权
    改进的锁定技术的装置和方法

    公开(公告)号：US20150074366A1

    公开(公告)日：2015-03-12

    申请号：US14024451

    申请日：2013-09-11

    申请人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

    发明人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

    IPC分类号： G06F9/46 ,  G06F12/14

    CPC分类号： G06F9/467 ,  G06F9/30181 ,  G06F9/526 ,  G06F12/1466

    摘要： An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.

    摘要翻译： 一种用于提高在事务存储架构内执行投机关键部分的效率的装置和方法。 例如，根据一个实施例的方法包括：等待执行程序代码的推测性临界部分，直到当前事务释放锁定为止; 在检测到锁已经被释放时响应地执行推测性关键部分以完成，而不管在推测性关键部分的执行期间锁是否被另一事务持有; 一旦投机关键部分的执行完成，确定是否采取锁定; 如果不采取锁定，则提交投机性关键部分，如果采取锁定，则中止推测性关键部分。

    TECHNOLOGIES FOR ROOT CAUSE IDENTIFICATION OF USE-AFTER-FREE MEMORY CORRUPTION BUGS
    13.
    发明申请
    TECHNOLOGIES FOR ROOT CAUSE IDENTIFICATION OF USE-AFTER-FREE MEMORY CORRUPTION BUGS 有权
    技术因素导致无使用内存损坏BUG的识别

    公开(公告)号：US20160283302A1

    公开(公告)日：2016-09-29

    申请号：US14670863

    申请日：2015-03-27

    申请人： Justin E. Gottschlich ,  Gilles A. Pokam ,  Cristiano L. Pereira

    发明人： Justin E. Gottschlich ,  Gilles A. Pokam ,  Cristiano L. Pereira

    IPC分类号： G06F11/07

    CPC分类号： G06F11/079 ,  G06F11/073

    摘要： Technologies for identification of a potential root cause of a use-after-free memory corruption bug of a program include a computing device to replay execution of the execution of the program based on an execution log of the program. The execution log comprises an ordered set of executed instructions of the program that resulted in the use-after-free memory corruption bug. The computing device compares a use-after-free memory address access of the program to a memory address associated with an occurrence of the use-after-free memory corruption bug in response to detecting the use-after-free memory address access and records the use-after-free memory address access of the program as a candidate for a root cause of the use-after-free memory corruption bug to a candidate list in response to detecting a match between the use-after-free memory address access of the program and the memory address associated with the occurrence of the use-after-free memory corruption bug.

    摘要翻译： 用于识别程序的无使用存储器内存损坏错误的潜在根本原因的技术包括基于程序的执行日志来重放执行程序的计算设备。 执行日志包括导致使用随机存储器损坏错误的程序的执行指令的有序集合。 计算装置响应于检测到使用无存储器存储器地址访问而将程序的无用空闲存储器地址访问与与使用无释放存储器损坏错误的发生相关联的存储器地址进行比较，并且记录 响应于检测到所述无用存储器内存地址访问之间的匹配，将所述程序的无用空闲内存地址访问作为候选列表的候选者，作为所述无用存储器内存损坏错误的根本原因 程序和与使用随机存储器内存损坏错误的发生相关联的存储器地址。

    TRANSACTIONAL MEMORY MANAGEMENT TECHNIQUES
    14.
    发明申请
    TRANSACTIONAL MEMORY MANAGEMENT TECHNIQUES 有权
    交易记忆管理技术

    公开(公告)号：US20150100741A1

    公开(公告)日：2015-04-09

    申请号：US14129936

    申请日：2013-07-15

    申请人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

    发明人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

    IPC分类号： G06F9/46

    CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/44 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0813

    摘要： Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

    摘要翻译： 描述了改进的事务性内存管理技术。 在一个实施例中，例如，设备可以包括处理器元件，用于由处理器元件执行以根据事务存储器进程同时执行软件事务和硬件事务的执行部件，用于由处理器元件执行的跟踪部件 激活全局锁以指示软件事务正在执行;以及最终化组件，用于由处理器元件执行以提交软件事务，并且在执行软件事务完成时停用全局锁定，终止组件中止硬件 当执行硬件事务完成时，全局锁活动时的事务。 描述和要求保护其他实施例。

    MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS
    15.
    发明申请
    MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS 有权
    促进计算机系统软件程序中指导性原子动力的动态和有效管理的机制

    公开(公告)号：US20140281705A1

    公开(公告)日：2014-09-18

    申请号：US13977690

    申请日：2013-03-15

    申请人： Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne

    发明人： Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne

    IPC分类号： G06F11/14

    CPC分类号： G06F9/30145 ,  G06F9/3009 ,  G06F9/3895 ,  G06F9/3897 ,  G06F9/52 ,  G06F11/0724 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3636

    摘要： A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

    摘要翻译： 描述了根据一个实施例的用于促进软件程序中的指令原子性违规的动态和有效管理的机制。 如本文所述的实施例的方法包括在来自记录系统的重放逻辑处接收运行第一宏指令的第一软件线程的记录和运行第二宏指令的第二软件线程。 第一软件线程和第二软件线程分别由计算设备处理器的第一核心和第二核心执行。 记录系统可以记录第一和第二宏指令之间的交织。 该方法包括在发生时准确地重播第一和第二宏指令的交错记录。 正确重放可以包括重播第一和第二宏指令的本地存储器状态以及第一和第二软件线程的全局存储器状态。

    Methods and apparatus to manage concurrent predicate expressions
    19.
    发明授权
    Methods and apparatus to manage concurrent predicate expressions 有权
    管理并发谓词表达式的方法和设备

    公开(公告)号：US09117021B2

    公开(公告)日：2015-08-25

    申请号：US13827121

    申请日：2013-03-14

    申请人： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

    发明人： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

    IPC分类号： G06F11/36

    CPC分类号： G06F9/52 ,  G06F11/3632

    摘要： Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

    摘要翻译： 公开了方法，装置，系统和制品以管理并发谓词表达。 一种示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行 直到满足第一条件，并且当满足第二条件时识别并发冲突。

    UNBOUNDED TRANSACTIONAL MEMORY WITH FORWARD PROGRESS GUARANTEES USING A HARDWARE GLOBAL LOCK
    20.
    发明申请
    UNBOUNDED TRANSACTIONAL MEMORY WITH FORWARD PROGRESS GUARANTEES USING A HARDWARE GLOBAL LOCK 有权
    使用硬件全局锁定的前进进程保护的无关紧要的交易记忆

    公开(公告)号：US20150169362A1

    公开(公告)日：2015-06-18

    申请号：US14108892

    申请日：2013-12-17

    申请人： Justin E. Gottschlich ,  Irina Calciu ,  Tatiana Shpeisman ,  Gilles A. Pokam

    发明人： Justin E. Gottschlich ,  Irina Calciu ,  Tatiana Shpeisman ,  Gilles A. Pokam

    IPC分类号： G06F9/46 ,  G06F12/14

    CPC分类号： G06F9/467 ,  G06F9/52 ,  G06F9/528

    摘要： A processing device implementing unbounded transactional memory with forward progress guarantees using a hardware global lock is disclosed. A processing device of the disclosure includes a hardware transactional memory (HTM) hardware contention manager to cause a bounded transaction to be translated to an unbounded transaction, the unbounded transaction to acquire a global hardware lock for the unbounded transaction, the global hardware lock read by bounded transactions that abort when the global hardware lock is taken. The processing device further includes an execution unit communicably coupled to the HTM hardware contention manager to execute instructions of the unbounded transaction without speculation, the unbounded transaction to release the global hardware lock upon completion of execution of the instructions.

    摘要翻译： 公开了一种使用硬件全局锁来实现具有前进进度的无界事务存储器的处理设备。 本公开的处理装置包括硬件事务存储器（HTM）硬件竞争管理器，用于使有界事务被转换为无界事务，该无界事务获取无界事务的全局硬件锁，全局硬件锁由 全局硬件锁定时中止的有界事务。 处理装置还包括执行单元，其可通信地耦合到HTM硬件争用管理器以执行无界事务的指令而无需推测，该无限制事务在完成指令的执行时释放全局硬件锁定。