Abstract:
Techniques for determining the voltage-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining voltage-dependent capacitance of a circuit comprises measuring a parameter of the circuit at each one of a plurality of voltages, and, for each voltage, determining a capacitance of the circuit at the voltage by fitting a resistor-capacitor (RC) model of the circuit to the measured parameter of the circuit at the voltage.
Abstract:
Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that the sensor circuit receives the endpoint's data signal and clock signal. The sensor circuit introduces skew between the data signal and the clock signal by delaying the data signal more than the clock signal, and compares skewed data signals to determine if an error occurs because of the induced skew. By delaying the data signal with different delay amounts and monitoring what delays cause errors, an amount of timing slack in the data signal and clock signal (e.g., margin to criticality) is measured during operation of the chip for relevant circuitry to the system implemented on the chip, compared to test circuitry operating while the chip is in a test mode.
Abstract:
Techniques for estimating state-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining a circuit state for a circuit comprises determining a capacitance of the circuit for each one of a plurality of circuit states, and selecting one of the circuit states based on the determined capacitances.
Abstract:
In one embodiment, an apparatus comprises a capacitor and a die. The die comprises a resistor switch coupled between a power line and the capacitor, wherein the resistor switch has an adjustable resistance, and the power line and the capacitor are both external to the die. The die also comprises a circuit configured to receive power from the power line, and a controller configured to open the resistor switch if the power line is powered down.
Abstract:
In one embodiment, a temperature management system comprises a plurality of thermal sensors at different locations on a chip, and a temperature manager. The temperature manager is configured to receive a plurality of temperature readings from the thermal sensors, to fit a quadratic temperature model to the received temperature readings, and to estimate a hotspot temperature on the chip using the fitted quadratic temperature model.
Abstract:
In one embodiment, a method of temperature control comprises receiving temperature readings from a temperature sensor on a chip, calculating one or more second derivatives of temperature with respect to time based on the temperature readings, and determining whether to perform temperature mitigation on the chip based on the one or more calculated second derivatives of temperature.
Abstract:
Techniques for estimating state-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining a circuit state for a circuit comprises determining a capacitance of the circuit for each one of a plurality of circuit states, and selecting one of the circuit states based on the determined capacitances.
Abstract:
In one embodiment, a temperature management system comprises a plurality of thermal sensors at different locations on a chip, and a temperature manager. The temperature manager is configured to receive a plurality of temperature readings from the thermal sensors, to fit a quadratic temperature model to the received temperature readings, and to estimate a hotspot temperature on the chip using the fitted quadratic temperature model.
Abstract:
Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.
Abstract:
A method of setting a supply voltage in a device is disclosed. The method includes receiving a first plurality of inputs from a plurality of sensors that are representative of a gate delay of a signal path on the device, and receiving a second plurality of inputs from a plurality of temperature sensors. The method further includes estimating a plurality of interconnect delays for the signal path based on the second plurality of inputs, and determining the supply voltage for the signal path based on the first plurality of inputs and the plurality of interconnect delays.