公开(公告)号：US20140266353A1

公开(公告)日：2014-09-18

申请号：US13842481

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Yi Tang ,  Bo Sun

IPC: H03M1/50 ,  H03L7/099 ,  H03L7/06

CPC classification number: H03M1/50 ,  G04F10/005 ,  H03L7/08 ,  H03L7/0991 ,  H03L2207/50

Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.

Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。

公开(公告)号：US20140266127A1

公开(公告)日：2014-09-18

申请号：US13802725

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Bo Sun

IPC: G05F3/08

CPC classification number: G05F3/08 ,  G01R15/04 ,  G01R15/08 ,  G01R15/09 ,  G01R19/16519 ,  G01R19/16552 ,  G05F1/465

Abstract: A voltage divider circuit is provided that automatically and dynamically adjusts its voltage divider chains as a supply voltage changes. The voltage divider circuit includes a plurality of voltage divider branches having different divider factors to divide the supply voltage and obtain a divided supply voltage. Additionally, a control circuit is coupled to the plurality of voltage divider branches and adapted to automatically monitor the supply voltage and dynamically select a voltage divider branch from among the plurality of voltage divider branches to maintain a selected divided supply voltage within a pre-determined voltage range.

Abstract translation: 提供了一个分压电路，可以随着电源电压的变化自动动态地调节分压器的电压。 分压器电路包括具有不同分频器因数的多个分压器分支，以分割电源电压并获得分开的电源电压。 此外，控制电路耦合到多个分压器分支并且适于自动监测电源电压并且从多个分压器分支中动态地选择分压器分支，以将所选择的分压电源电压维持在预定电压内 范围。

公开(公告)号：US10536165B1

公开(公告)日：2020-01-14

申请号：US16280985

申请日：2019-02-20

Applicant: QUALCOMM Incorporated

Inventor： Anand Gaurav ,  Bo Sun

IPC: H03M9/00 ,  H04J1/08

Abstract: In certain aspects, a serial-to-parallel converter includes multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, wherein each of the stages includes one or more demultiplexers. The serial-to-parallel converter also includes demultiplexer control circuits, wherein each of the demultiplexer control circuits is coupled to the one or more demultiplexers of a respective one of the stages, and a pattern detector coupled to the demultiplexer control circuits.

公开(公告)号：US10270455B2

公开(公告)日：2019-04-23

申请号：US15436930

申请日：2017-02-20

Applicant: QUALCOMM Incorporated

Inventor： Bo Sun

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/081

Abstract: Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled delay line and a phase error detector circuit. Tap nodes are provided from outputs of one or more delay circuits in the controlled delay line. To detect and correct for phase errors in the controlled delay line, a phase detection circuit is provided that includes at least two phase detectors each configured to measure a phase offset error between tap nodes from the delay circuit(s) in the controlled delay line. These phase errors are then combined to create an error correction signal, which is used to control the delay of the delay circuit(s) in the controlled delay line to lock the phase of the output of the final delay circuit to an input reference clock signal.

公开(公告)号：US10063366B2

公开(公告)日：2018-08-28

申请号：US15269320

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Marco Zanuso ,  Giovanni Marucci ,  Tsai-Pi Hung ,  Francesco Gatta ,  Bo Sun

IPC: H03D3/24 ,  H04L7/033 ,  H04W72/04 ,  H04B1/40 ,  H03L7/08 ,  H03L7/197 ,  H04B1/713

CPC classification number: H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

公开(公告)号：US10024818B2

公开(公告)日：2018-07-17

申请号：US15186409

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Aparin ,  Bo Sun ,  Joung Won Park

IPC: G01N27/414 ,  G01N27/417

Abstract: An ionic current sensor array includes a master bias generator and a plurality of sensing cells. The master bias generator is configured to generate a bias voltage. Each sensing cell includes an ionic current sensor, an integrating capacitor, a sense transistor coupled between the integrating capacitor and the ionic current sensor, and an amplifier coupled to provide a reference voltage to bias the ionic current sensor. The amplifier includes a first transistor and a second transistor. The first transistor is coupled to receive the bias voltage, and the second transistor is coupled to the first transistor to provide the reference voltage to the ionic current sensor. The second transistor is also coupled between a source of the sense transistor and the gate of the sense transistor.

公开(公告)号：US09100026B2

公开(公告)日：2015-08-04

申请号：US13938727

申请日：2013-07-10

Applicant: QUALCOMM Incorporated

Inventor： Gary John Ballantyne ,  Bo Sun ,  Yi Tang ,  Zixiang Yang ,  Masoud Ensafdaran

IPC: H03L7/099 ,  H03B5/12 ,  H03J5/24

CPC classification number: H03L7/0991 ,  H03B5/1265 ,  H03B2200/0088 ,  H03B2201/025 ,  H03B2202/017 ,  H03J5/24 ,  H03J2200/10 ,  H03J2200/36 ,  H03L7/099 ,  H03L2207/50

Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

Abstract translation: 一个特征涉及包含可变电容器和降噪电路的数字控制振荡器（DCO）。 可变电容器具有控制DCO的输出频率的可变电容值。 可变电容值基于由第一电容器组提供的第一组电容值，由第二电容器组提供的第二组电容值和由辅助电容器组提供的辅助组电容值。 噪声降低电路适于通过调整辅助电容电容值来调节可变电容值，同时保持第一组电容值和/或第二组电容值中的至少一个基本上不变。 在调整可变电容值之前，噪声降低电路可以确定接收的输入DCO控制字在电容器组敏感边界之间转变。

公开(公告)号：US10560105B1

公开(公告)日：2020-02-11

申请号：US16175610

申请日：2018-10-30

Applicant: QUALCOMM Incorporated

Inventor： Bo Sun

IPC: H03L7/08 ,  H03L7/081 ,  H03K5/14 ,  H04L7/00 ,  H04L7/033 ,  H03L7/093 ,  H03K5/00

Abstract: A delay-locked loop (DLL) is provided that includes both a first delay line and a second delay line. The delay-locked loop functions to synchronize a DLL output clock signal relative to a received clock signal using the first delay line while a phase difference between the received clock signal and a received data signal corresponds to a delay within an operating range for the first delay line. As the phase difference increases to force the first delay line out of its operating range, the delay-locked loop transitions to using the second delay line to synchronize the DLL output clock signal relative to the received clock signal.

公开(公告)号：US20150085902A1

公开(公告)日：2015-03-26

申请号：US14034243

申请日：2013-09-23

Applicant: QUALCOMM INCORPORATED

Inventor： Daniel Keyes Butterfield ,  Sumit Verma ,  Jeremy Darren Dunworth ,  Bo Sun

IPC: H03M1/12 ,  H04B1/38

CPC classification number: H03M1/1245 ,  H03M3/344 ,  H03M3/504 ,  H04B1/0007 ,  H04B1/04 ,  H04B1/38

Abstract: A transmitter includes a delta-sigma modulator characterized by a noise transfer function having a multitude of zeroes positioned substantially near a frequency band of a receive signal. The transmitter further includes, in part, a multi-phase digital-to-analog (DAC) converter converting an output signal of the delta-sigma modulator to an analog signal. The DAC is characterized by a transfer function that passes the desired signal to its output and attenuates a multitude of images of the sampling clock signal. The transmitter transmits at a frequency defined by an odd multiple of a fraction of the sampling clock signal frequency. The DAC includes a number of stages each pair of which is associated with one of the images being attenuated. The delta-sigma modulator includes a multitude of stages each associated with a different one of the zeroes. Each stage of said delta-sigma modulator optionally receives three tap coefficients.

Abstract translation: 发射机包括Δ-Σ调制器，其特征在于具有基本上接近接收信号的频带的多个零的噪声传递函数。 发射机还部分地包括将Δ-Σ调制器的输出信号转换为模拟信号的多相数模（DAC）转换器。 DAC的特征在于将所需信号传递到其输出并衰减采样时钟信号的大量图像的传递函数。 发射机以由采样时钟信号频率的一部分的奇数倍定义的频率发射。 DAC包括多个阶段，每个阶段与被衰减的图像中的一个相关联。 Δ-Σ调制器包括多个级，其各自与不同的一个零相关联。 所述Δ-Σ调制器的每个级可任选地接收三个抽头系数。