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    RUN-LENGTH DETECTION AND CORRECTION
    11.
    发明申请
    RUN-LENGTH DETECTION AND CORRECTION 有权
    运行长度检测和校正

    公开(公告)号：US20150043358A1

    公开(公告)日：2015-02-12

    申请号：US14453287

    申请日：2014-08-06

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Chulkyu Lee

    IPC: H04L1/00 ,  H04L12/26

    CPC classification number: H04L1/0056 ,  H04L1/0014 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L43/0811

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. The apparatus may determine whether a run-length violation will occur or is likely to occur if a first sequence of symbols provided by a mapper of an M-Wire N-Phase encoder is transmitted on a plurality of wires. A second sequence of symbols may be substituted for the first sequence of symbols. The second sequence of symbols may comprise a surplus sequence of symbols that is not used for mapping data in the mapper.

    Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 如果由M-Wire N相编码器的映射器提供的第一符号序列在多个导线上传输，则装置可以确定是否会发生游程长度违规或可能发生游程长度违例。 符号的第二序列可以代替第一符号序列。 第二符号序列可以包括不用于映射器中的数据的多余符号序列。

    C-PHY half-rate wire state encoder and decoder
    12.
    发明授权
    C-PHY half-rate wire state encoder and decoder 有权

    公开(公告)号：US11240077B2

    公开(公告)日：2022-02-01

    申请号：US17070219

    申请日：2020-10-14

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Ying Duan ,  Shih-Wei Chou

    IPC: H04L25/49 ,  H04L25/493 ,  H04L7/00 ,  H04L25/14 ,  H04L25/02

    Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

    Analog-mixed signal circuit cells with universal Fin pitch and poly pitch
    13.
    发明授权
    Analog-mixed signal circuit cells with universal Fin pitch and poly pitch 有权

    公开(公告)号：US10978437B2

    公开(公告)日：2021-04-13

    申请号：US16456311

    申请日：2019-06-28

    Applicant: QUALCOMM Incorporated

    Inventor： Jonathan Holland ,  Jeffrey Charles Lee ,  Chulkyu Lee ,  Harikrishna Chintarlapalli Reddy

    IPC: H01L27/02 ,  H01L27/06 ,  H01L23/528 ,  H03K17/687 ,  H03F3/45 ,  H01L29/78 ,  H01L49/02

    Abstract: An integrated circuit, comprising a transistor-based cell comprising a set of fin field effect transistors (Fin FETs) chained together in a first direction, wherein the set of Fin FETs include fins extending longitudinally along the first direction and equally-spaced apart in a second direction orthogonal to the first direction by a fin pitch, and a set of polysilicon gates extending longitudinally along the second direction and equally-spaced apart in the first direction by a poly pitch, wherein a first dimension of the transistor-based cell along the first direction is substantially a first integer multiplied by the poly pitch, and wherein a second dimension of the transistor-based cell along the second direction is substantially a second integer multiplied by the fin pitch. The integrated circuit may include other non-transistor-based cells (e.g., passive cells), such as thin-film resistor or capacitor cells, which are arranged in a two-dimensional array with the transistor-based cell.

    LOW POWER PHYSICAL LAYER DRIVER TOPOLOGIES
    14.
    发明申请
    LOW POWER PHYSICAL LAYER DRIVER TOPOLOGIES 审中-公开

    公开(公告)号：US20180234122A1

    公开(公告)日：2018-08-16

    申请号：US15950779

    申请日：2018-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shih-Wei Chou ,  Chulkyu Lee ,  Dhaval Sejpal

    IPC: H04B1/04 ,  H04L25/493 ,  H04L25/02 ,  H04B3/52 ,  G06F13/40

    CPC classification number: H04B1/04 ,  G06F13/4072 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/493

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.

    N-PHASE PHASE AND POLARITY ENCODED SERIAL INTERFACE
    18.
    发明申请
    N-PHASE PHASE AND POLARITY ENCODED SERIAL INTERFACE 有权

    公开(公告)号：US20180006846A1

    公开(公告)日：2018-01-04

    申请号：US15598000

    申请日：2017-05-17

    Applicant: QUALCOMM Incorporated

    Inventor： George Wiley ,  Glenn Raskin ,  Chulkyu Lee

    IPC: H04L25/02 ,  H04L5/20 ,  H04L25/49

    CPC classification number: H04L25/0272 ,  H04L5/20 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L25/4917

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

    FEED-FORWARD BIAS CIRCUIT
    19.
    发明申请
    FEED-FORWARD BIAS CIRCUIT 有权
    进给前进偏置电路

    公开(公告)号：US20170077907A1

    公开(公告)日：2017-03-16

    申请号：US14384374

    申请日：2014-05-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： Wenjun Su ,  Chulkyu Lee ,  Le Zhang ,  Guangming Yin

    IPC: H03K3/011 ,  G05F3/26 ,  H03K5/159

    CPC classification number: H03K3/011 ,  G05F1/00 ,  G05F3/205 ,  G05F3/242 ,  G05F3/262 ,  H02M3/07 ,  H03K5/159 ,  H03K17/145 ,  H03K19/00384 ,  H03K2217/0018

    Abstract: A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

    Abstract translation: 前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。 在一些方面，前馈偏置电路通过在不同的拐角条件下产生不同的偏置信号来补偿电路中的晶体管工艺角。 在一些实现中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

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