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公开(公告)号：US09319218B2
公开(公告)日：2016-04-19
申请号：US14315142
申请日：2014-06-25
Applicant: QUALCOMM Incorporated
Inventor： Shree Krishna Pandey , Arun Chandra Kundu , George Alan Wiley , Chulkyu Lee
CPC classification number: H04L7/0041 , H04B3/00 , H04B3/462 , H04B3/542 , H04L25/0264
Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.
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公开(公告)号：US20160099817A1
公开(公告)日：2016-04-07
申请号：US14966236
申请日：2015-12-11
Applicant: QUALCOMM Incorporated
Inventor： George Alan Wiley , Glenn Raskin , Chulkyu Lee
CPC classification number: H04L25/0272 , H04L5/20 , H04L25/0282 , H04L25/0294 , H04L25/0298 , H04L25/4917
Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.
Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 数据以多位符号编码，并且多位符号在多个连接器上传输。 可以通过将符号映射到多个连接器的状态序列来传输多比特符号，并且根据状态序列来驱动连接器。 状态序列的定时可以在连续状态之间的每个转换处在接收器处确定。 每个连接器的状态可以由在每个连接器上传输的多相信号的极性和旋转方向来定义。
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公开(公告)号：US09112815B2
公开(公告)日：2015-08-18
申请号：US13662076
申请日：2012-10-26
Applicant: Qualcomm Incorporated
Inventor： George Alan Wiley
IPC: G06F15/16 , H04L12/911 , H04L12/12
CPC classification number: H04L47/745 , H04L12/12 , Y02D50/40
Abstract: System, methods and apparatus are described that facilitate data link shutdown between two devices within an electronic apparatus, enabling safe entry into a hibernation mode. A host device transmits a command to a client device over a first data link. If the client device is not transmitting over the second data link, the host devices initiates shut down of the first data link and entry to a hibernation state. A delay may be initiated when it is determined that the client device is transmitting on the second data link. The command may comprise an instruction revoking permission to transmit data over a second data link to cause the client device to terminate communication on the second data link.
Abstract translation: 描述了促进电子设备内的两个设备之间的数据链路关闭的系统，方法和装置，使得能够安全地进入休眠模式。 主机设备通过第一数据链路向客户端设备发送命令。 如果客户端设备不是通过第二数据链路发送，则主机设备启动关闭第一数据链路并进入休眠状态。 当确定客户端设备正在第二数据链路上发送时，可以启动延迟。 该命令可以包括撤消通过第二数据链路发送数据的许可的指令，以使客户端设备终止在第二数据链路上的通信。
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公开(公告)号：US09071220B2
公开(公告)日：2015-06-30
申请号：US13832990
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Chulkyu Lee , Joseph Cheung
CPC classification number: H03H2/005 , H04B1/04 , H04L25/0272 , H04L25/0278 , H04L25/14 , Y02D30/30
Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.
Abstract translation: 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。
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公开(公告)号：US20150098538A1
公开(公告)日：2015-04-09
申请号：US14507702
申请日：2014-10-06
Applicant: QUALCOMM Incorporated
Inventor： George Alan Wiley , Chulkyu Lee
IPC: H04L7/04
CPC classification number: H04L7/042 , H04L1/205 , H04L1/206 , H04L1/247 , H04L5/20 , H04L25/0272 , H04L25/0282 , H04L25/0294 , H04L25/0298 , H04L25/4917
Abstract: System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols may be generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.
Abstract translation: 描述了便于与多线，多相通信链路相关的测试和测量的系统，方法和装置。 信息以N相极性编码符号发送，并且可以生成与符号相对应的眼图，使得符号与对应于用于采样符号的时钟边缘的每个符号的触发对齐。 眼图可以用于确定通信链路中的建立时间的充分性以及定义通信信道能力的其它这样的特性。
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Patent Agency Ranking
公开(公告)号：US20150023454A1
公开(公告)日：2015-01-22
申请号：US14336977
申请日：2014-07-21
Applicant: QUALCOMM Incorporated
Inventor： Chulkyu Lee , George Alan Wiley , Richard Dominic Wietfeldt
IPC: H04L7/00
CPC classification number: H04L7/033 , G06F13/4295 , H04B3/50 , H04L7/00 , H04L7/0037 , H04L7/0041
Abstract: Systems and methods for multi-phase signaling are described herein. In one embodiment, a method for receiving data comprises receiving a sequence of symbols from a plurality of conductors, and generating a clock signal by detecting transitions in the received sequence of symbols. The method also comprises delaying the received sequence of symbols, and capturing one or more symbols in the delayed sequence of symbols using the clock signal, wherein a previous symbol in the delayed sequence of symbols is captured using a clock pulse in the clock signal generated based on a detected transition to a current symbol in the received sequence of symbols.
Abstract translation: 本文描述了用于多相信令的系统和方法。 在一个实施例中，一种用于接收数据的方法包括从多个导体接收符号序列，以及通过检测所接收的符号序列中的转变来产生时钟信号。 该方法还包括延迟接收到的符号序列，并使用时钟信号捕获延迟符号序列中的一个或多个符号，其中使用基于时钟信号生成的时钟信号中的时钟脉冲来捕获延迟符号序列中的先前符号 在所接收的符号序列中检测到到当前符号的转换。
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公开(公告)号：US20140372642A1
公开(公告)日：2014-12-18
申请号：US14302359
申请日：2014-06-11
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
IPC: G06F13/42
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.
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公开(公告)号：US09998300B2
公开(公告)日：2018-06-12
申请号：US15598000
申请日：2017-05-17
Applicant: QUALCOMM Incorporated
Inventor： George Alan Wiley , Glenn Raskin , Chulkyu Lee
CPC classification number: H04L25/0272 , H04L5/20 , H04L25/0282 , H04L25/0294 , H04L25/0298 , H04L25/4917
Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.
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公开(公告)号：US09948485B2
公开(公告)日：2018-04-17
申请号：US15013003
申请日：2016-02-02
Applicant: QUALCOMM Incorporated
Inventor： George Alan Wiley
CPC classification number: H04L25/4917 , H04L5/20 , H04L7/033 , H04L25/0272 , H04L25/0282 , H04L25/0294 , H04L25/0298 , H04L27/22
Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.
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公开(公告)号：US09811499B2
公开(公告)日：2017-11-07
申请号：US15486217
申请日：2017-04-12
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
IPC: G06F13/42 , G06F13/364
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. Other described devices may be configured as a bus master or as a slave. In one method, a transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.
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