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    TECHNIQUE OF LINK STATE DETECTION AND WAKEUP IN POWER STATE OBLIVIOUS INTERFACE
    14.
    发明申请
    TECHNIQUE OF LINK STATE DETECTION AND WAKEUP IN POWER STATE OBLIVIOUS INTERFACE 有权
    链路状态检测技术在电源状态下的异常接口

    公开(公告)号：US20160259702A1

    公开(公告)日：2016-09-08

    申请号：US15060221

    申请日：2016-03-03

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  George Alan Wiley ,  Amit Gil

    IPC: G06F11/30 ,  G06F15/17 ,  G06F1/32 ,  G06F9/44 ,  G06F15/78

    CPC classification number: G06F11/3051 ,  G06F1/3209 ,  G06F1/3278 ,  G06F9/4418 ,  G06F11/3041 ,  G06F15/17 ,  G06F15/7807 ,  Y02D10/157

    Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a hit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message, Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

    Abstract translation: 描述了便于第一设备向第二设备发送/重发消息的系统，方法和设备。 第一设备向第二设备发送第一消息。 然后，第一设备接收第二消息并识别指示第二消息的发起者的第二消息的命中。 如果该比特指示第一个设备作为第二个消息的发起者，则第二个消息是第一个消息的回应，回应的接收表明第二个设备处于睡眠状态。 因此，第一设备等待第二设备唤醒并将第一消息重新发送到第二设备，以确保在第一消息的原始传输期间（当第二设备睡着时）丢失的任何分组现在在第二设备 已知醒来。

    COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYER
    17.
    发明申请
    COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYER 审中-公开
    外围组件互连（PCI）EXPRESS（PCIe）交易层的协同驱动增强

    公开(公告)号：US20160371222A1

    公开(公告)日：2016-12-22

    申请号：US15184181

    申请日：2016-06-16

    Applicant: QUALCOMM Incorporated

    Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg

    IPC: G06F13/42 ,  G06F13/40 ,  G06F12/08

    CPC classification number: G06F13/4282 ,  G06F12/0828 ,  G06F12/1441 ,  G06F13/4022 ,  G06F15/167 ,  G06F21/00 ,  G06F2212/621 ,  G06F2213/0026

    Abstract: Coherency driven enhancements to a PCIe transaction layer are disclosed. In an exemplary aspect, a coherency agent is added to a PCIe system to support a relaxed consistency model for use of memory therein. In particular, endpoints can request ownership of portions of the memory to read from and write to the memory. The coherency agent assigns an address range including the requested portions. The requesting endpoint copies the contents of the memory corresponding to the assigned address range into local endpoint memory to perform read and write operations locally. The owning endpoint may provide an updated snapshot of the copied memory contents upon request. At completion of use of the copied memory contents, or upon request from the coherency agent, ownership of the address range reverts back to the root complex, and the endpoint sends the updated contents back to the address range in the system memory element.

    Abstract translation: 公开了对PCIe事务层的一致性驱动增强。 在示例性方面，将一致性代理添加到PCIe系统以支持用于其中的存储器的松弛一致性模型。 特别地，端点可以请求存储器的部分的所有权从存储器读取和写入存储器。 一致性代理分配包括所请求部分的地址范围。 请求端点将对应于分配的地址范围的内存的内容复制到本地端点存储器中，以在本地执行读写操作。 所拥有的端点可以根据请求提供复制的存储器内容的更新的快照。 在完成使用复制的存储器内容时，或者根据来自一致性代理的请求，地址范围的所有权返回到根复合体，并且端点将更新的内容发送回系统存储器元件中的地址范围。

    COMMUNICATING TRANSACTION-SPECIFIC ATTRIBUTES IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SYSTEM
    18.
    发明申请
    COMMUNICATING TRANSACTION-SPECIFIC ATTRIBUTES IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SYSTEM 审中-公开
    在外围组件互连显式（PCIE）系统中交流交互特定属性

    公开(公告)号：US20160371221A1

    公开(公告)日：2016-12-22

    申请号：US15168574

    申请日：2016-05-31

    Applicant: QUALCOMM Incorporated

    Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

    IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

    CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/4022 ,  G06F2213/0026

    Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

    Abstract translation: 披露外围组件互连快递（PCIe）系统中的交易特定属性的通信。 PCIe系统包括主机系统和至少一个PCIe端点。 PCIe端点配置为确定可以提高预定义主机事务的效率和性能的一个或多个特定于事务的属性。 在这方面，在一方面，PCIe端点对至少一个PCIe TLP的事务层分组（TLP）前缀中的事务特定属性进行编码，并将PCIe TLP提供给主机系统。 在另一方面，主机系统中的PCIe根复合体（RC）被配置为从PCIe端点接收的PCIe TLP的TLP前缀中检测并提取特定于事务的属性。 通过传递PCIe TLP的TLP前缀中的特定于交易的属性，可以在不违反现有PCIe标准的情况下提高PCIe系统的效率和性能。

    Low power PCIe
    20.
    发明授权
    Low power PCIe 有权

    公开(公告)号：US10963035B2

    公开(公告)日：2021-03-30

    申请号：US16155824

    申请日：2018-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  James Lionel Panian ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad ,  Amit Gil ,  Shaul Yohai Yifrach

    IPC: G06F1/3234 ,  G06F13/40 ,  G06F13/10 ,  G06F1/3206

    Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

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