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    AMPLIFIER WITH SWITCHABLE COMMON GATE GAIN BUFFER
    11.
    发明申请
    AMPLIFIER WITH SWITCHABLE COMMON GATE GAIN BUFFER 有权
    具有可切换公共门增益缓冲器的放大器

    公开(公告)号：US20140197886A1

    公开(公告)日：2014-07-17

    申请号：US13899091

    申请日：2013-05-21

    Applicant: QUALCOMM Incorporated

    Inventor： Rajagopalan Rangarajan ,  Chirag D. Patel

    IPC: H03F3/217

    CPC classification number: H03F3/2171 ,  H03F3/72 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/3052

    Abstract: An amplifier having a switchable common gate gain buffer is disclosed. In an exemplary embodiment, an apparatus includes a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics. At least two gain channels utilize transistors having different transconductance values. The apparatus also includes at least one impedance network coupled to at least one gain channel to provide the constant input impedance.

    Abstract translation: 公开了具有可切换公共栅极增益缓冲器的放大器。 在示例性实施例中，一种装置包括多个可选择的增益通道，其在公共输入处提供恒定的输入阻抗以接收输入信号并产生具有选定的增益和电流特性中的至少一个的输出信号。 至少两个增益通道利用具有不同跨导值的晶体管。 该装置还包括耦合到至少一个增益通道以提供恒定输入阻抗的至少一个阻抗网络。

    Polyphase filter with interphase coupling
    12.
    发明授权
    Polyphase filter with interphase coupling 有权

    公开(公告)号：US11632098B2

    公开(公告)日：2023-04-18

    申请号：US17211716

    申请日：2021-03-24

    Applicant: Qualcomm Incorporated

    Inventor： Timothy Donald Gathman ,  Lai Kan Leung ,  Chirag Dipak Patel ,  Xinmin Yu ,  Rajagopalan Rangarajan

    IPC: H03H11/22 ,  H03H11/04

    Abstract: An example apparatus includes a polyphase transconductance-capacitor filter. The polyphase filter includes a DC bias voltage node, a plus in-phase filter unit, a minus in-phase filter unit, a plus quadrature-phase filter unit, and a minus quadrature-phase filter unit. Each filter unit respectively includes an input node, an output node, and a control node. The polyphase filter also includes a plus in-phase switch and a minus in-phase switch. The plus in-phase switch is coupled to the control node of the plus in-phase filter unit, the DC bias voltage node, and the input node of one or both of the plus quadrature-phase filter unit and the minus quadrature-phase filter unit. The minus in-phase switch is coupled to the control node of the minus in-phase filter unit, the DC bias voltage node, and the input node of one or both of the plus quadrature-phase filter unit and the minus quadrature-phase filter unit.

    Avoiding Spurious Responses with Reconfigurable LO Dividers
    17.
    发明申请
    Avoiding Spurious Responses with Reconfigurable LO Dividers 有权
    用可重配置的分频器避免杂散响应

    公开(公告)号：US20150334711A1

    公开(公告)日：2015-11-19

    申请号：US14644677

    申请日：2015-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Rajagopalan Rangarajan ,  Chiewcharn Narathong ,  Lai Kan Leung ,  Dongling Pan ,  Aleksandar Miodrag Tasic ,  Yiwu Tang

    IPC: H04W72/04 ,  H04W88/06 ,  H04L12/709

    CPC classification number: H04W72/0453 ,  H04B1/005 ,  H04B15/06 ,  H04L45/245 ,  H04W88/06

    Abstract: Methods and apparatus including: setting up a plurality of configurations for a plurality of local oscillator (LO) paths of a carrier aggregation (CA) transceiver operating with a plurality of bands; calculating and comparing frequencies for each LO path of the plurality of LO paths and at least one divider ratio of LO dividers for each band of the plurality of bands to identify frequency conflicts; and reconfiguring the LO dividers for the plurality of LO paths and the plurality of bands when the frequency conflicts are identified.

    Abstract translation: 一种方法和装置，包括：为多个频带操作的载波聚合（CA）收发机的多个本地振荡器（LO）路径建立多个配置; 计算和比较所述多个LO路径中的每个LO路径的频率和所述多个频带中的每个频带的LO分频器的至少一个分频比，以识别频率冲突; 以及当识别出频率冲突时，为多个LO路径和多个频带重新配置LO分频器。

    Phase-locked loop (PLL) with multiple error determiners
    19.
    发明授权
    Phase-locked loop (PLL) with multiple error determiners 有权

    公开(公告)号：US11025260B1

    公开(公告)日：2021-06-01

    申请号：US17003923

    申请日：2020-08-26

    Applicant: Qualcomm Incorporated

    Inventor： Yue Chao ,  Marco Zanuso ,  Rajagopalan Rangarajan ,  Yiwu Tang

    IPC: H03L7/099 ,  H03L7/197 ,  H03L7/089 ,  H03L7/093

    Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.

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