公开(公告)号：US20210409029A1

公开(公告)日：2021-12-30

申请号：US17357478

申请日：2021-06-24

Applicant: Qualcomm Incorporated

Inventor： Masoud Moslehi Bajestan ,  Marco Zanuso ,  Razak Hossain ,  Hasnain Lakdawala

IPC: H03L7/099 ,  H03L7/091 ,  H03L7/081 ,  H03L7/18

Abstract: An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.

公开(公告)号：US11290058B2

公开(公告)日：2022-03-29

申请号：US17076998

申请日：2020-10-22

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Chao ,  Yinghan Wang ,  Marco Zanuso ,  Rajagopalan Rangarajan

IPC: H03B5/12 ,  H03L7/093 ,  H03L7/08

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

公开(公告)号：US11025260B1

公开(公告)日：2021-06-01

申请号：US17003923

申请日：2020-08-26

Applicant: Qualcomm Incorporated

Inventor： Yue Chao ,  Marco Zanuso ,  Rajagopalan Rangarajan ,  Yiwu Tang

IPC: H03L7/099 ,  H03L7/197 ,  H03L7/089 ,  H03L7/093

Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.

公开(公告)号：US11595028B2

公开(公告)日：2023-02-28

申请号：US17362509

申请日：2021-06-29

Applicant: Qualcomm Incorporated

Inventor： Masoud Moslehi Bajestan ,  Marco Zanuso ,  Razak Hossain ,  Hasnain Lakdawala

IPC: H03K3/017 ,  H03L7/093 ,  H01Q1/24

Abstract: An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

公开(公告)号：US20210409007A1

公开(公告)日：2021-12-30

申请号：US17362509

申请日：2021-06-29

Applicant: Qualcomm Incorporated

Inventor： Masoud Moslehi Bajestan ,  Marco Zanuso ,  Razak Hossain ,  Hasnain Lakdawala

IPC: H03K3/017 ,  H03L7/093

Abstract: An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

公开(公告)号：US09893875B2

公开(公告)日：2018-02-13

申请号：US15270444

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Marco Zanuso ,  Mohammad Elbadry ,  Tsai-Pi Hung ,  Ravi Sridhara ,  Francesco Gatta ,  Jingcheng Zhuang

IPC: H03D3/24 ,  H04L7/033 ,  H04L29/06 ,  H04L5/14 ,  H03L7/14 ,  H03L7/197 ,  H04W84/04

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

公开(公告)号：US11411569B2

公开(公告)日：2022-08-09

申请号：US17357478

申请日：2021-06-24

Applicant: Qualcomm Incorporated

Inventor： Masoud Moslehi Bajestan ,  Marco Zanuso ,  Razak Hossain ,  Hasnain Lakdawala

IPC: H03L7/099 ,  H03L7/091 ,  H03L7/18 ,  H03L7/081

Abstract: An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.

公开(公告)号：US20190326915A1

公开(公告)日：2019-10-24

申请号：US15957441

申请日：2018-04-19

Applicant: Qualcomm Incorporated

Inventor： Masoud Moslehi Bajestan ,  Mehran Mohammadi Izad ,  Marco Zanuso

IPC: H03L7/089 ,  H03L7/099

Abstract: An apparatus is disclosed that implements a sampling phase-locked loop. In an example aspect, the apparatus includes a phase frequency detector, a relative phase signal determiner, a voltage-controlled oscillator (VCO), and a feedback path. The phase frequency detector is configured to produce a phase indication signal based on a reference signal and a feedback signal. The relative phase signal determiner is coupled to the phase frequency detector and includes a sampler. The relative phase signal determiner is configured to determine a relative phase signal based on the phase indication signal using the sampler. The VCO is coupled to the relative phase signal determiner and is configured to produce an oscillating signal based on the relative phase signal. The feedback path is disposed between the VCO and the phase frequency detector. The feedback path is configured to provide the feedback signal to the phase frequency detector using the oscillating signal.

公开(公告)号：US11411567B2

公开(公告)日：2022-08-09

申请号：US17117240

申请日：2020-12-10

Applicant: QUALCOMM INCORPORATED

Inventor： Masoud Moslehi Bajestan ,  Giovanni Marucci ,  Dongmin Park ,  Marco Zanuso ,  Yiwu Tang

IPC: H03L7/099 ,  H03J7/04 ,  H03L7/02 ,  H03L7/093 ,  H03M3/00 ,  H03K3/037

Abstract: A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

公开(公告)号：US11336288B1

公开(公告)日：2022-05-17

申请号：US17315337

申请日：2021-05-09

Applicant: Qualcomm Incorporated

Inventor： Hung-Chuan Pai ,  Marco Zanuso

IPC: H03L7/089 ,  H03L7/093

Abstract: An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source, a second current source, and a first switch coupled between the first current source and the second current source. The filter is coupled to the charge pump between the first switch and the second current source. The second switch is coupled to the charge pump between the first current source and the first switch. The buffer is coupled between the filter and the second switch, with the buffer comprising a voltage buffer.