公开(公告)号：US08958226B2

公开(公告)日：2015-02-17

申请号：US13730524

申请日：2012-12-28

Applicant: Qualcomm Incorporated

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。

公开(公告)号：US08891273B2

公开(公告)日：2014-11-18

申请号：US13727494

申请日：2012-12-26

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Vattikonda ,  Nishith Desai ,  Changho Jung

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/04

Abstract: A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match.

Abstract translation: 三元内容可寻址存储器（TCAM）内的方法包括从当前TCAM级的上拉晶体管的栅极处和当前TCAM的下拉晶体管的栅极处接收来自先前TCAM级的匹配线输出 阶段。 当从前一个TCAM级输出的匹配线指示不匹配时，该方法通过下拉晶体管将当前TCAM级的匹配线条设置为低值。 当从前一个TCAM级输出的匹配线指示匹配时，该方法还通过上拉晶体管将当前TCAM级的匹配线条设置为高值。

公开(公告)号：US20140269112A1

公开(公告)日：2014-09-18

申请号：US13863989

申请日：2013-04-16

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。

公开(公告)号：US20180074126A1

公开(公告)日：2018-03-15

申请号：US15263059

申请日：2016-09-12

Applicant: QUALCOMM Incorporated

Inventor： Bilal Zafar ,  Rakesh Vattikonda ,  De Lu ,  Venkatasubramanian Narayanan ,  Masoud Zamani ,  Joseph Fang

IPC: G01R31/317 ,  G11C7/22 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

公开(公告)号：US20180006650A1

公开(公告)日：2018-01-04

申请号：US15367706

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K19/0185 ,  H03K19/00 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356113 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/0013

Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

公开(公告)号：US09432022B2

公开(公告)日：2016-08-30

申请号：US14257212

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Frank Guo ,  Rakesh Vattikonda

IPC: H03L5/00 ,  H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/356182

Abstract: A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.

Abstract translation: 电平移位器具有根据输入信号的二进制状态选择性地削弱或加强的PMOS堆叠。

公开(公告)号：US09082481B2

公开(公告)日：2015-07-14

申请号：US14503861

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

公开(公告)号：US09030893B2

公开(公告)日：2015-05-12

申请号：US13760988

申请日：2013-02-06

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Nishith Desai ,  Rakesh Vattikonda

IPC: G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/419 ,  G11C11/408 ,  G11C5/14

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/00 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/419

Abstract: A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP≧VddM>VddMlower.

Abstract translation: 提供一种写辅助驱动器电路，即使当电源电压降低时，也可以在写入操作中帮助存储器单元（例如，易失性存储器位单元）来保持存储器核心处的电压足够高以用于正确的写入操作。 写辅助驱动器电路可以被配置为在待机操作模式期间向位单元核提供存储器电源电压VddM。 在写入操作模式中，写入辅助驱动器电路可以向位单元核心以及本地写入位线（lwbl）和本地写入位线条（lwblb）中的至少一个提供降低的存储器电源电压VddMlower。 此外，写辅助驱动器电路还可以向本地写入字线（lww1）提供外围电源电压VddP，其中VddP≥VddM> VddMlower。

公开(公告)号：US20140254293A1

公开(公告)日：2014-09-11

申请号：US13784830

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Nishith Desai ,  Rakesh Vattikonda ,  Changho Jung

IPC: G11C7/12

CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/417 ,  G11C2207/2227

Abstract: Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation.

Abstract translation: 本文提供了能够在双电压域存储器架构中有效操作的快速，高能量写入驱动器的各个方面。 具体来说，这里描述的写入驱动器的各个方面将高速驱动器与电压电平转换能力相结合，可以在减少使用较低功耗的硅片区域的同时有效地实现。 写驱动器电路移位或调整第一电压域与第二电压域之间的电压电平。 在一个示例中，写驱动器电路耦合到耦合到SRAM存储器的一个或多个位单元的全局写位线和本地写位线。 写入驱动器电路在写操作期间将全局写位线处的第一电压电平转换为本地写位线处的第二电压电平。

公开(公告)号：US20140185349A1

公开(公告)日：2014-07-03

申请号：US13730524

申请日：2012-12-28

Applicant: QUALCOMM INCORPORATED

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。