公开(公告)号：US09331712B1

公开(公告)日：2016-05-03

申请号：US14832732

申请日：2015-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： Adrienne Milner ,  Amin Ansari ,  Richard Senior ,  Vito Remo Bica

IPC: H03M5/00 ,  H03M7/40 ,  H03M7/48

CPC classification number: H03M7/4062 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/4006 ,  H03M7/42 ,  H03M7/48 ,  H04N19/423 ,  H04N19/91

Abstract: Data compression systems, methods, and computer program products are disclosed. For each successive input word of an input stream, it is determined whether the input word matches an entry in a lookback table. The lookback table is updated in response to the input word. Input words may be of a number of data types, including zero runs and full or partial matches with an entry in the lookback table. A codeword is generated by entropy encoding a data type corresponding to the input word. The lookback table may be indexed by the position of the input word in the input stream.

公开(公告)号：US11868244B2

公开(公告)日：2024-01-09

申请号：US17572471

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/401

Abstract: A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region and a second cache line from a low priority data region. The system also includes a compression circuit for compressing the cache lines to obtain a first and a second compressed cache line. The system also includes a cache line packing circuit for packing the compressed cache lines such that the first compressed cache line is written to a first predetermined portion and the second cache line or a portion of the second compressed cache line is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

公开(公告)号：US10482021B2

公开(公告)日：2019-11-19

申请号：US15193001

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Richard Senior ,  Anand Janakiraman

IPC: G06F12/0871 ,  G06F12/0868

Abstract: In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time.

公开(公告)号：US10169246B2

公开(公告)日：2019-01-01

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1036

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：US20180329830A1

公开(公告)日：2018-11-15

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/1045 ,  G06F3/06

CPC classification number: G06F12/1036 ,  G06F3/06 ,  G06F3/0608 ,  G06F3/0661 ,  G06F3/0685 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/60

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：US09998143B2

公开(公告)日：2018-06-12

申请号：US15230325

申请日：2016-08-05

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Amin Ansari ,  Jinxia Bai ,  Vito Bica

IPC: H03M7/30

CPC classification number: H03M7/3088 ,  H03M7/30 ,  H03M7/3086 ,  H03M7/6005

Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.

公开(公告)号：US20170269851A1

公开(公告)日：2017-09-21

申请号：US15074444

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Amin Ansari ,  Richard Senior ,  Nieyan Geng ,  Anand Janakiraman ,  Gurvinder Singh Chhabra

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0611 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0615 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/401 ,  G06F2212/65

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

公开(公告)号：US09600420B2

公开(公告)日：2017-03-21

申请号：US14526868

申请日：2014-10-29

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Richard Senior ,  Raghuveer Raghavendra ,  Nieyan Geng ,  Gurvinder Singh Chhabra

IPC: G06F12/00 ,  G06F12/12 ,  G06F12/10 ,  H03M7/30 ,  G06F12/08

CPC classification number: G06F12/12 ,  G06F12/08 ,  G06F12/1009 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/6017 ,  H03M7/6023 ,  H03M7/702

Abstract: Aspects include computing devices, systems, and methods for implementing executing decompression of a compressed page. A computing device may determine a decompression block of a compressed page that contains a code instruction requested in a memory access request. Decompression blocks, other than the decompression block containing the requested code instruction, may be selected for decompression based on being situated between an end of the compressed page and the decompression block containing the requested code instruction. Decompression blocks not identified for decompression may be substituted for a fault or exception code. The computing device may decompress decompression blocks identified for decompression, starting at the end of the compressed page and terminating the decompression of the compressed page upon filling all blocks with decompressed blocks, faults, or exception code. The remaining decompression blocks of the compressed page may be decompressed after or concurrently with the execution of the requested code instruction.

公开(公告)号：US11386012B1

公开(公告)日：2022-07-12

申请号：US17201247

申请日：2021-03-15

Applicant: QUALCOMM incorporated

Inventor： Arvind Krishnaswamy ,  Richard Senior ,  Sundeep Kushwaha ,  Can Acar

IPC: G06F12/00 ,  G06F12/0882 ,  G06F12/0871 ,  G06F9/32 ,  G06F12/02

Abstract: Various embodiments include methods and devices for generating a memory map configured to map virtual addresses of pages to physical addresses, in which pages of a same size are grouped into regions. The embodiments may include adding a first entry for a first additional page to a first region in the memory map, shifting virtual addresses of the first region to accommodate a shift of virtual addresses of the first region allocated for code by a sub-page granular shift amount, mapping shifted virtual addresses of the first entry for the first additional page to physical address mapped to a first lowest shifted virtually addressed page of the first region, and shifting the virtual addresses of the first region allocated for code by a sub-page granular shift amount, in which the virtual addresses of the first region allocated for code partially shift into the first entry for the first additional page.

公开(公告)号：US10120581B2

公开(公告)日：2018-11-06

申请号：US15085399

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Amin Ansari ,  Vito Remo Bica ,  Jinxia Bai

IPC: G06F3/06 ,  H03M7/30

Abstract: Aspects for generating compressed data streams with lookback pre-fetch instructions are disclosed. A data compression system is provided and configured to receive and compress an uncompressed data stream as part of a lookback-based compression scheme. The data compression system determines if a current data block was previously compressed. If so, the data compression system is configured to insert a lookback instruction corresponding to the current data block into the compressed data stream. Each lookback instruction includes a lookback buffer index that points to an entry in a lookback buffer where decompressed data corresponding to the data block will be stored during a separate decompression scheme. Once the data blocks have been compressed, the data compression system is configured to move a lookback buffer index of each lookback instruction in the compressed data stream into a lookback pre-fetch instruction located earlier than the corresponding lookback instruction in the compressed data stream.