公开(公告)号：US11782762B2

公开(公告)日：2023-10-10

申请号：US16801776

申请日：2020-02-26

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Sundeep Kushwaha ,  Harsha Gordhan Jagasia ,  Christopher Ahn ,  Gurvinder Singh Chhabra ,  Nieyan Geng ,  Maksim Krasnyanskiy ,  Unni Prasad

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F12/0806

CPC classification number: G06F9/5016 ,  G06F9/4806 ,  G06F9/5022 ,  G06F12/0806 ,  G06F2209/481 ,  G06F2209/503 ,  G06F2212/1021

Abstract: A method of managing a stack includes detecting, by a stack manager of a processor, that a size of a frame to be allocated exceeds available space of a first stack. The first stack is used by a particular task executing at the processor. The method also includes designating a second stack for use by the particular task. The method further includes copying metadata associated with the first stack to the second stack. The metadata enables the stack manager to transition from the second stack to the first stack upon detection that the second stack is no longer in use by the particular task. The method also includes allocating the frame in the second stack.

公开(公告)号：US20180217930A1

公开(公告)日：2018-08-02

申请号：US15420667

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/0808 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/128 ,  G06F2212/401 ,  G06F2212/621 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.

公开(公告)号：US09413386B1

公开(公告)日：2016-08-09

申请号：US14626905

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Amin Ansari ,  Jinxia Bai ,  Vito Bica

IPC: H03M7/30

CPC classification number: H03M7/3088 ,  H03M7/30 ,  H03M7/3086 ,  H03M7/6005

Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.

Abstract translation: 用于数据解压缩的系统可以包括耦合到具有存储在其上的远程字典的远程存储器的处理器，并且耦合到具有本地字典的本地存储器的解压缩逻辑。 处理器可以在执行期间通过访问本地字典来解压缩数据，并且如果需要，可以对远程字典进行解压缩。

公开(公告)号：US09344114B1

公开(公告)日：2016-05-17

申请号：US14832739

申请日：2015-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： Adrienne Milner ,  Amin Ansari ,  Richard Senior ,  Vito Remo Bica

IPC: H03M7/38 ,  H03M7/40 ,  H03M7/48 ,  H03M7/30 ,  H04N19/61

CPC classification number: H03M7/4062 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/4006 ,  H03M7/42 ,  H03M7/48 ,  H04N19/423 ,  H04N19/91

Abstract: Data compression systems, methods, and computer program products are disclosed. For each successive input word of an input stream, it is determined whether the input word matches an entry in a lookback table. The lookback table is updated in response to the input word. Input words may be of a number of data types, including zero runs and full or partial matches with an entry in the lookback table. A codeword is generated by entropy encoding a data type corresponding to the input word. The lookback table may be indexed by the position of the input word in the input stream.

Abstract translation: 公开了数据压缩系统，方法和计算机程序产品。 对于输入流的每个连续输入字，确定输入字是否与回溯表中的条目匹配。 响应于输入字更新回溯表。 输入字可以是数据类型的数量，包括零运行，以及与回溯表中的条目的完全或部分匹配。 通过对对应于输入字的数据类型进行熵编码来生成码字。 回溯表可以由输入流中的输入字的位置索引。

公开(公告)号：US09300320B2

公开(公告)日：2016-03-29

申请号：US14318564

申请日：2014-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Amin Ansari ,  Vito Bica ,  Richard Senior

IPC: H03M7/30 ,  H04N19/00 ,  G06F12/08

CPC classification number: H03M7/3064 ,  G06F12/0886 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/6058 ,  H04N19/00

Abstract: A multi-pass compression iteratively removes combinations of bits from locations in each word of a cache line of an uncompressed data stream. For each combination of removed bits, the remaining bits in the word values of the cache line are analyzed to generate a compression score. A highest compression score triggers the building of a dictionary from the remaining bits in the word values of the cache line. After a dictionary is built, the method may continue iteratively to create subsequent dictionaries from the words that remain uncompressed in the cache line. To decompress a word, a first bit section of the compressed word is used to identify a dictionary that is then queried for bits indexed in a second bit section of the compressed word. The uncompressed word is reconstructed by interleaving the queried bits with the removed combination of bits from a third bit section of the word.

Abstract translation: 多遍压缩迭代地从未压缩的数据流的高速缓存线的每个字中的位置中去除位的组合。 对于删除位的每个组合，分析高速缓存行的字值中的剩余位以产生压缩分数。 最高的压缩分数触发从高速缓存行的单词值中的其余位构建字典。 在构建字典之后，该方法可以继续迭代地从在高速缓存行中保持未压缩的单词创建后续字典。 为了对字进行解压缩，使用压缩字的第一比特部分来识别字典，然后在压缩字的第二比特部分中对索引的比特进行查询。 通过将查询的比特与从单词的第三比特部分中去除的比特组合进行交织来重构未压缩的单词。

公开(公告)号：US11829292B1

公开(公告)日：2023-11-28

申请号：US17572472

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/084 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0811

Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.

公开(公告)号：US11687461B1

公开(公告)日：2023-06-27

申请号：US17572472

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/084 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0811

Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.

公开(公告)号：US10198362B2

公开(公告)日：2019-02-05

申请号：US15426473

申请日：2017-02-07

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/08 ,  G06F12/128 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/0897

Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.

公开(公告)号：US09823854B2

公开(公告)日：2017-11-21

申请号：US15074444

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Amin Ansari ,  Richard Senior ,  Nieyan Geng ,  Anand Janakiraman ,  Gurvinder Singh Chhabra

IPC: G06F3/06 ,  G06F12/0897

CPC classification number: G06F3/0611 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0615 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/401 ,  G06F2212/65

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

公开(公告)号：US20170285939A1

公开(公告)日：2017-10-05

申请号：US15085399

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Amin Ansari ,  Vito Remo Bica ,  Jinxia Bai

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0673 ,  H03M7/3086 ,  H03M7/6017 ,  H03M7/6029

Abstract: Aspects for generating compressed data streams with lookback pre-fetch instructions are disclosed. A data compression system is provided and configured to receive and compress an uncompressed data stream as part of a lookback-based compression scheme. The data compression system determines if a current data block was previously compressed. If so, the data compression system is configured to insert a lookback instruction corresponding to the current data block into the compressed data stream. Each lookback instruction includes a lookback buffer index that points to an entry in a lookback buffer where decompressed data corresponding to the data block will be stored during a separate decompression scheme. Once the data blocks have been compressed, the data compression system is configured to move a lookback buffer index of each lookback instruction in the compressed data stream into a lookback pre-fetch instruction located earlier than the corresponding lookback instruction in the compressed data stream.