公开(公告)号：US20220199152A1

公开(公告)日：2022-06-23

申请号：US17131172

申请日：2020-12-22

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/418 ,  G06F3/06

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A column multiplexer selects from a plurality of columns using a pair of pass transistor for each column. The column multiplexer drives a true input node and a complement input node of an output data latch.

公开(公告)号：US20220093171A1

公开(公告)日：2022-03-24

申请号：US17028965

申请日：2020-09-22

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Chulmin JUNG

IPC: G11C11/419

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

公开(公告)号：US20210350865A1

公开(公告)日：2021-11-11

申请号：US16868402

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Bin LIANG ,  Chi-Jui CHEN

IPC: G11C29/02 ,  G11C29/20 ,  G11C29/10 ,  G11C29/12 ,  G11C29/44 ,  G11C29/00

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

公开(公告)号：US20210134358A1

公开(公告)日：2021-05-06

申请号：US17144077

申请日：2021-01-07

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Keejong KIM ,  Chulmin JUNG ,  Ritu CHABA

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US20230395139A1

公开(公告)日：2023-12-07

申请号：US17833852

申请日：2022-06-06

Applicant: QUALCOMM Incorporated

Inventor： Dhvani SHETH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US20230223075A1

公开(公告)日：2023-07-13

申请号：US18175023

申请日：2023-02-27

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/413 ,  H03K19/20

CPC classification number: G11C11/419 ,  G11C11/413 ,  H03K19/20

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

公开(公告)号：US20230179183A1

公开(公告)日：2023-06-08

申请号：US17922176

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Chulmin JUNG

IPC: H03K3/012 ,  H03K5/01 ,  H03K17/56

CPC classification number: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K2005/00078

Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

公开(公告)号：US20230093852A1

公开(公告)日：2023-03-30

申请号：US17448846

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Chulmin JUNG

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G11C5/14 ,  H03K19/21

Abstract: A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.

公开(公告)号：US20190095295A1

公开(公告)日：2019-03-28

申请号：US15713557

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad AHMED ,  Chulmin JUNG ,  Sei Seung YOON ,  Esin TERZIOGLU

IPC: G06F11/20

Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

公开(公告)号：US20170221551A1

公开(公告)日：2017-08-03

申请号：US15013897

申请日：2016-02-02

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Fahad AHMED ,  Sei Seung YOON ,  Keejong KIM

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C7/02 ,  G11C5/06 ,  G11C7/00 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/026 ,  G11C29/14 ,  G11C29/50012

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.