公开(公告)号：US20170213587A1

公开(公告)日：2017-07-27

申请号：US15003444

申请日：2016-01-21

Applicant: QUALCOMM Incorporated

Inventor： Sharad Kumar Gupta ,  Mukund Narasimhan ,  Veerabhadra Rao Boda

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C7/227 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/229

Abstract: A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

公开(公告)号：US09607674B1

公开(公告)日：2017-03-28

申请号：US14989750

申请日：2016-01-06

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Veerabhadra Rao Boda

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F1/04 ,  G11C5/14 ,  G11C7/02 ,  G11C7/20 ,  H03K3/356173 ,  H03K5/135

Abstract: A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal in a first power domain and initiate a second clock signal in a second power domain in response to the first clock signal. The first power domain provides a first voltage for logic operations and the second power domain provides a second voltage for memory operations. The apparatus includes a tracking circuit configured to generate a reset signal based on a voltage level of the first power domain. The reset signal may be configured to reset the pulse generator in the first power domain. The apparatus may further include a latch configured to receive the second clock signal in the second power domain.

公开(公告)号：US11971741B2

公开(公告)日：2024-04-30

申请号：US17396046

申请日：2021-08-06

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Murali Krishna Ade ,  Arun David Arul Diraviyam ,  Mayank Gupta ,  Boris Dimitrov Andreev

IPC: G06F1/10 ,  G06F1/12 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F1/10 ,  G06F1/12 ,  G06F9/30134 ,  G06F9/544

Abstract: Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

公开(公告)号：US20200372939A1

公开(公告)日：2020-11-26

申请号：US16421365

申请日：2019-05-23

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C7/06 ,  G11C7/10

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

公开(公告)号：US10147483B1

公开(公告)日：2018-12-04

申请号：US15708818

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Mukund Narasimhan ,  Rakesh Kumar Sinha ,  Raghav Gupta

IPC: G11C11/00 ,  G11C11/419

Abstract: Systems, methods, and apparatus for writing data into a static random access memory (SRAM) are provided. A write driver circuit includes a bitcell array, a bitline coupled to the bitcell array, and a first driving circuit configured to drive the bitline via a write driver node for writing data into a bitcell for a write operation. The write driver circuit also includes a pre-charging circuit configured to control or to operate with the write driver circuit to drive the write driver node to a high voltage level or a low voltage level for the write operation, and pre-charge the write driver node to the high voltage level, and float the write driver node for a bit-masking operation.

公开(公告)号：US09916892B1

公开(公告)日：2018-03-13

申请号：US15448526

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Mukund Narasimhan ,  Fahad Ahmed ,  Chulmin Jung

IPC: G11C11/419 ,  G11C5/14 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.

公开(公告)号：US09837144B1

公开(公告)日：2017-12-05

申请号：US15408086

申请日：2017-01-17

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Kumar Sinha ,  Mukund Narasimhan ,  Sharad Kumar Gupta

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1009 ,  G11C7/1096 ,  G11C7/12

Abstract: A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.