公开(公告)号：US09614081B2

公开(公告)日：2017-04-04

申请号：US15201744

申请日：2016-07-05

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/78 ,  H01L29/49 ,  H01L27/108 ,  H01L27/11 ,  H01L21/8234

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US09112013B2

公开(公告)日：2015-08-18

申请号：US13785674

申请日：2013-03-05

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu Sayama

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66477 ,  H01L29/66659 ,  H01L29/7835

Abstract: Provided are a semiconductor device having a high breakdown voltage and attaining the restraint of the action of a parasite bipolar transistor, and a method for producing the device. A high-breakdown-voltage p-channel-type transistor included in the semiconductor device has a first n-type semiconductor layer arranged in a semiconductor substrate and at a main-surface-side (upside) of a p-type region in the semiconductor substrate, and a local n-type buried region arranged just below a first p-type dopant region to contact the first n-type semiconductor layer.

Abstract translation: 提供具有高击穿电压并实现寄生双极晶体管的作用的限制的半导体器件及其制造方法。 包括在半导体器件中的高耐压p沟道型晶体管具有布置在半导体衬底中的第一n型半导体层和半导体中的p型区域的主表面侧（上侧） 衬底和布置在第一p型掺杂剂区域正下方的接触第一n型半导体层的局部n型掩埋区域。

公开(公告)号：US08742497B2

公开(公告)日：2014-06-03

申请号：US13861005

申请日：2013-04-11

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu Sayama

IPC: H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device is provided, in which work of a parasitic bipolar transistor can be suppressed and a potential difference can be provided between a source region and a back gate region. A high voltage tolerant transistor formed over a semiconductor substrate includes: a well region of a first conductivity type; a first impurity region as the source region; and a second impurity region as a drain region. The semiconductor device further includes a third impurity region and a gate electrode for isolation. The third impurity region is formed, in planar view, between a pair of the first impurity regions, and from which a potential of the well region is extracted. The gate electrode for isolation is formed over the main surface between the first impurity region and the third impurity region.

Abstract translation: 提供了一种半导体器件，其中可以抑制寄生双极晶体管的工作，并且可以在源极区域和后栅极区域之间提供电位差。 形成在半导体衬底上的耐高压晶体管包括：第一导电类型的阱区; 第一杂质区域作为源区; 以及作为漏极区域的第二杂质区域。 半导体器件还包括用于隔离的第三杂质区和栅电极。 第三杂质区域在平面图中形成在一对第一杂质区域之间，并且从其中提取阱区域的电位。 用于隔离的栅电极形成在第一杂质区和第三杂质区之间的主表面上。

公开(公告)号：US20140113418A1

公开(公告)日：2014-04-24

申请号：US14140168

申请日：2013-12-24

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu Ota ,  Hirokazu Sayama ,  Hidekazu Oda

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US08541272B2

公开(公告)日：2013-09-24

申请号：US13833891

申请日：2013-03-15

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu Ota ,  Hirokazu Sayama ,  Hidekazu Oda

IPC: H01L21/8238

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US12288760B2

公开(公告)日：2025-04-29

申请号：US17835541

申请日：2022-06-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki Igarashi ,  Hirokazu Sayama

IPC: H01L23/00

Abstract: A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

公开(公告)号：US09412867B2

公开(公告)日：2016-08-09

申请号：US14933079

申请日：2015-11-05

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/11 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US08809186B2

公开(公告)日：2014-08-19

申请号：US14038981

申请日：2013-09-27

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/44

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 用于形成nMOS晶体管的非绝缘硅栅极绝缘膜和栅电极设置在硅衬底上。 使用栅电极作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此栅极电极 非晶化 随后，提供氧化硅膜以覆盖栅电极，其温度小于栅电极发生再结晶的温度。 此后，在约1000℃的温度下进行热处理，由此在栅极上施加高的压缩残余应力，并且对栅电极下方的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US12198987B2

公开(公告)日：2025-01-14

申请号：US17353079

申请日：2021-06-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US09349816B2

公开(公告)日：2016-05-24

申请号：US14931000

申请日：2015-11-03

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu Ota ,  Hirokazu Sayama ,  Hidekazu Oda

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).