公开(公告)号：US20250015138A1

公开(公告)日：2025-01-09

申请号：US18892925

申请日：2024-09-23

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210028306A1

公开(公告)日：2021-01-28

申请号：US17060486

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US20190027597A1

公开(公告)日：2019-01-24

申请号：US16137279

申请日：2018-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasunori YAMASHITA ,  Koichi ARAI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51

Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.

公开(公告)号：US20160035904A1

公开(公告)日：2016-02-04

申请号：US14870922

申请日：2015-09-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI

IPC: H01L29/808 ,  H01L27/098 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L29/8083 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66037

Abstract: In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

Abstract translation: 为了确保杂质扩散率低于硅基的SiC基JFET的性能，确保栅极深度，同时精确地控制栅极区域之间的距离，而不是通过离子注入形成栅极区域到侧壁 的沟渠 这意味着由栅极距离和栅极深度限定的沟道区域应具有高的纵横比。 此外，由于处理的限制，在源极区域内形成栅极区域。 在源极和栅极区域之间形成高度掺杂的PN结导致各种问题，例如结电流的不可避免的增加。 此外，为了形成端接结构，需要显着高能量的离子注入。 在本发明中，提供了一种垂直沟道型SiC功率JFET，其具有位于源极区域之下和栅极区域之下并与源极区分离的浮动栅极区域。

公开(公告)号：US20240290881A1

公开(公告)日：2024-08-29

申请号：US18638883

申请日：2024-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0274 ,  H01L29/0696 ,  H01L29/45 ,  H01L29/4916

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210217888A1

公开(公告)日：2021-07-15

申请号：US17216136

申请日：2021-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20190288105A1

公开(公告)日：2019-09-19

申请号：US16282981

申请日：2019-02-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266 ,  H01L21/308

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US20160099316A1

公开(公告)日：2016-04-07

申请号：US14873185

申请日：2015-10-01

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Kenichi HISADA

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

Abstract translation: 在具有沟槽型MOS栅极结构的碳化硅半导体器件中，本发明使得可以抑制工作特性变化。 通过将p型杂质的角度离子注入到通过注入具有不同的注入能量的离子形成的p型体层而形成具有在沟槽的侧壁部分处的深度方向上均匀的杂质浓度分布的p型沟道层 在沟槽形成之后彼此相隔两次或更多次。 此外，虽然当通过成角度的离子注入形成p型沟道层时，p型杂质也被引入到沟槽底部的n型漂移层中，通过形成沟道长度来规定n 杂质浓度高于p型沟道层，p型体层和p型体层与n型漂移层之间的n型漂移层的杂质浓度 。 通过这些措施，可以抑制工作特性的变化。

公开(公告)号：US20140346528A1

公开(公告)日：2014-11-27

申请号：US14270469

申请日：2014-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI

IPC: H01L29/16 ,  H01L29/808 ,  H01L29/66

CPC classification number: H01L29/8083 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66037

Abstract: In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

Abstract translation: 为了确保杂质扩散率低于硅基的SiC基JFET的性能，确保栅极深度，同时精确地控制栅极区域之间的距离，而不是通过离子注入形成栅极区域到侧壁 的沟渠 这意味着由栅极距离和栅极深度限定的沟道区域应具有高的纵横比。 此外，由于处理的限制，在源极区域内形成栅极区域。 在源极和栅极区域之间形成高度掺杂的PN结导致各种问题，例如结电流的不可避免的增加。 此外，为了形成端接结构，需要显着高能量的离子注入。 在本发明中，提供了一种垂直沟道型SiC功率JFET，其具有位于源极区域之下和栅极区域之下并与源极区分离的浮动栅极区域。