公开(公告)号：US20170039160A1

公开(公告)日：2017-02-09

申请号：US14915621

申请日：2015-03-12

Applicant: Renesas Electronics Corporation

Inventor： Takahiko SUGIMOTO ,  Tomohiro UNE ,  Hiroshi UEDA ,  Ryoji HASHIMOTO ,  Toshiyuki KAYA

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/00 ,  G06F13/4009 ,  G06F13/4027

Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.

Abstract translation: 数据选择器电路将包括多种类型的数据的数据组划分成多种类型的数据。 第一压缩电路和第二压缩电路根据多种类型的数据分别彼此并行地压缩多种类型的数据。 第一压缩电路压缩数据并获得压缩数据。 第二压缩电路压缩数据并获得压缩数据。 数据传输电路将压缩数据和压缩数据发送到终端。

公开(公告)号：US20160283430A1

公开(公告)日：2016-09-29

申请号：US14965612

申请日：2015-12-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi UEDA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Kenichi IWATA ,  Katsushige MATSUBARA

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4068 ,  G06F9/5066 ,  G06F13/28 ,  H04N19/176 ,  H04N19/423 ,  H04N19/436

Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).

Abstract translation: 提供在处理单元之间传送数据的多个传送模块（402-0至402-M），以分别对应于多个处理单元（401-0至401-M）。 对于每个处理单元（401-0至401-M），第一环形总线（403-0至403-M）连接相应处理单元内的子单元和对应于处理单元的传送模块，从而形成 环形。 多个传送模块（402-0至402-M）被连接成使得它们通过第二环形总线（404）形成环形。

公开(公告)号：US20150245045A1

公开(公告)日：2015-08-27

申请号：US14620081

申请日：2015-02-11

Applicant: Renesas Electronics Corporation

Inventor： Katsushige MATSUBARA ,  Takayuki MATSUMI ,  Seiji MOCHIZUKI ,  Kenichi IWATA ,  Toshiyuki KAYA

IPC: H04N19/436 ,  H04N19/91 ,  G06T1/20

CPC classification number: H04N19/436 ,  G06T1/20 ,  H04N19/91

Abstract: The present invention provides an image processing apparatus capable of efficiently scheduling tasks and a control method for the same. An image processing apparatus according to an embodiment includes: a request receiving unit that receives requests from a plurality of pieces of content; a variable-length code processing unit which decodes or encodes the content; a plurality of image signal processing units executing tasks according to the requests in parallel; an estimating unit that estimates estimate time by which a process of the task is completed in each of the image signal processing units on the basis of a parameter of decoding or encoding used in the variable-length code processing unit; and a scheduling unit that schedules tasks executed by the plurality of image signal processing units on the basis of estimation time estimated by the estimating unit.

Abstract translation: 本发明提供能够有效地调度任务的图像处理装置及其控制方法。 根据实施例的图像处理装置包括：请求接收单元，其从多个内容接收请求; 可变长度码处理单元，其对内容进行解码或编码; 多个图像信号处理单元，根据请求并行执行任务; 估计单元，其基于在所述可变长度代码处理单元中使用的解码或编码的参数来估计每个所述图像信号处理单元中完成所述任务的处理的估计时间; 以及调度单元，其基于由所述估计单元估计的估计时间来调度由所述多个图像信号处理单元执行的任务。

公开(公告)号：US20200073806A1

公开(公告)日：2020-03-05

申请号：US16446195

申请日：2019-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki HAYAKAWA ,  Toshiyuki KAYA ,  Shinichi SHIBAHARA

IPC: G06F12/0815 ,  G06F12/06

Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

公开(公告)号：US20180343461A1

公开(公告)日：2018-11-29

申请号：US16053244

申请日：2018-08-02

Applicant: Renesas Electronics Corporation

Inventor： Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Hiroshi UEDA ,  Tetsuya SHIBAYAMA

IPC: H04N19/46 ,  H04N19/65 ,  H04N17/00 ,  H04N19/44 ,  H04N19/89

CPC classification number: H04N19/46 ,  H04N17/004 ,  H04N19/44 ,  H04N19/65 ,  H04N19/89

Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.

公开(公告)号：US20180288418A1

公开(公告)日：2018-10-04

申请号：US16001559

申请日：2018-06-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ren IMAOKA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Kazushi AKIE ,  Ryoji HASHIMOTO

IPC: H04N19/139 ,  H04N19/137 ,  H04N19/132 ,  H04N19/172 ,  H04N19/124 ,  H04N19/105 ,  H04N19/61

Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.

公开(公告)号：US20180139460A1

公开(公告)日：2018-05-17

申请号：US15871629

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Keisuke MATSUMOTO ,  Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Hiroshi UEDA

IPC: H04N19/423 ,  H04N19/433 ,  H04N19/127 ,  H04N19/172 ,  H04N19/176 ,  H04N19/159 ,  H04N19/136 ,  H04N19/65 ,  H04N19/593 ,  H04N19/51 ,  H04N19/44 ,  H04N19/139

CPC classification number: H04N19/423 ,  H04N19/127 ,  H04N19/136 ,  H04N19/139 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/593 ,  H04N19/65

Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.

公开(公告)号：US20180077413A1

公开(公告)日：2018-03-15

申请号：US15699801

申请日：2017-09-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazushi AKIE ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Katsushige MATSUBARA ,  Hiroshi UEDA ,  Ren IMAOKA ,  Ryoji HASHIMOTO

IPC: H04N19/107 ,  H04N19/105 ,  H04N19/44 ,  H04N19/122 ,  H04N19/436 ,  H04N19/573 ,  H04N19/17 ,  G06T9/00

CPC classification number: H04N19/107 ,  G06T9/007 ,  H04N19/105 ,  H04N19/122 ,  H04N19/17 ,  H04N19/436 ,  H04N19/44 ,  H04N19/573 ,  H04N21/4728 ,  H04N21/816

Abstract: A display area can be smoothly moved.A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.

公开(公告)号：US20170365033A1

公开(公告)日：2017-12-21

申请号：US15690911

申请日：2017-08-30

Applicant: Renesas Electronics Corporation

Inventor： Toshiyuki KAYA ,  Katsushige Matsubara

IPC: G06T1/20 ,  H04N19/85 ,  H04N19/44 ,  G06F17/30 ,  H04N19/423

CPC classification number: G06T1/20 ,  G06F17/3028 ,  H04N19/423 ,  H04N19/44 ,  H04N19/85

Abstract: An image processing device includes a decoded data memory, a format-converted data memory, a decoder which decodes compressed image data in units of blocks, writes the decoded data in the blocks into the decoded data memory, and receives a notification that writing of the decoded data has been completed, and a progress notifier which is notified of completion of writing of the decoded data by the decoder, and generates and outputs upon completion of the decoding of a block of data or the writing of a block of the decoded data, a progress signal per picture.

公开(公告)号：US20170280155A1

公开(公告)日：2017-09-28

申请号：US15618316

申请日：2017-06-09

Applicant: Renesas Electronics Corporation

Inventor： Kenichi IWATA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Ryoji HASHIMOTO

IPC: H04N19/513 ,  H04N19/174 ,  H04N19/55 ,  H04N19/105 ,  H04N19/167

CPC classification number: H04N19/521 ,  H04N19/105 ,  H04N19/167 ,  H04N19/174 ,  H04N19/436 ,  H04N19/51 ,  H04N19/55 ,  H04N19/86

Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.