公开(公告)号：US20160308022A1

公开(公告)日：2016-10-20

申请号：US15198395

申请日：2016-06-30

Applicant: Renesas Electronics Corporation

Inventor： Yuta IKEGAMI ,  Tsuyoshi KACHI

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/308 ,  H01L21/321 ,  H01L21/8222 ,  H01L21/306

CPC classification number: H01L29/66348 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/32105 ,  H01L21/76895 ,  H01L21/8222 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/7397

Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.

Abstract translation: 在半导体器件的性能方面实现了改进。 在IGBT的n型基极用半导体基板的主表面上形成绝缘层。 在绝缘层的沟槽中，在半导体衬底上形成n型半导体层，并且在半导体层的两侧，通过栅极绝缘膜形成栅电极。 在半导体层的上部形成p型基极的p型半导体区域和n型发射极的n +型半导体区域。 在栅电极下方存在绝缘层的部分。 与通过栅极绝缘膜面对半导体层的侧表面相对的栅电极的侧表面与绝缘层相邻。

公开(公告)号：US20140235020A1

公开(公告)日：2014-08-21

申请号：US14261497

申请日：2014-04-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke ARAI ,  Yoshito NAKAZAWA ,  Ikuo HARA ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO ,  Tsuyoshi TABATA

IPC: H01L29/66

CPC classification number: H01L29/66325 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract translation: 提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。 在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。 然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。 结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。

公开(公告)号：US20130187223A1

公开(公告)日：2013-07-25

申请号：US13792134

申请日：2013-03-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA ,  Yoshito NAKAZAWA ,  Tsuyoshi KACHI ,  Yuji YATSUDA

IPC: H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.