公开(公告)号：US20210151609A1

公开(公告)日：2021-05-20

申请号：US17084163

申请日：2020-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L29/792 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/78

Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

公开(公告)号：US20200051905A1

公开(公告)日：2020-02-13

申请号：US16655606

申请日：2019-10-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L23/522 ,  H01L27/11517 ,  H01L21/768 ,  H01L23/532 ,  H01L21/762 ,  H01L49/02 ,  H01L27/11573 ,  H01L29/94 ,  H01L27/12

Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

公开(公告)号：US20160118394A1

公开(公告)日：2016-04-28

申请号：US14989999

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L27/115 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20140242796A1

公开(公告)日：2014-08-28

申请号：US14079120

申请日：2013-11-13

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L21/3105 ,  H01L27/105 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20140209996A1

公开(公告)日：2014-07-31

申请号：US14242500

申请日：2014-04-01

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kota FUNAYAMA ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US20130113035A1

公开(公告)日：2013-05-09

申请号：US13726088

申请日：2012-12-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Keiichi HARAGUCHI

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/66833

Abstract: To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force.A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode.

Abstract translation: 提供一种能够通过抑制驱动力的降低来提高具有非易失性存储单元的半导体器件的可靠性的技术。 存储单元由具有包括具有p型导电性的导电膜的选择栅电极和具有包含具有p型导电性的导电膜的存储栅极的存储器pMIS的选择pMIS配置，并且在写入时 热电子从半导体衬底1的侧面注入电荷存储层，并且在擦除时，从存储栅电极向电荷存储层注入热孔。

公开(公告)号：US20200035693A1

公开(公告)日：2020-01-30

申请号：US16460476

申请日：2019-07-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA

IPC: H01L27/1158 ,  H01L27/11568 ,  H01L27/11565

Abstract: In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

公开(公告)号：US20200006526A1

公开(公告)日：2020-01-02

申请号：US16447457

申请日：2019-06-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L27/11568 ,  H01L27/11565 ,  H01L21/311

Abstract: A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.

公开(公告)号：US20180374924A1

公开(公告)日：2018-12-27

申请号：US15978296

申请日：2018-05-14

Applicant: Renesas Electronics Corporation

Inventor： Atsushi YOSHITOMI ,  Yoshiyuki KAWASHIMA

IPC: H01L29/423 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/792 ,  H01L29/78

CPC classification number: H01L29/4234 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42372 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/792

Abstract: To provide a semiconductor device having improved reliability by relaxing the unevenness of the injection distribution of electrons and holes into a charge accumulation film attributable to the shape of the fin of a MONOS memory comprised of a fin transistor. Of a memory gate electrode configuring a memory cell formed above a fin, a portion contiguous to an ONO film that covers the upper surface of the fin and a portion contiguous to the ONO film that covers the side surface of the fin are made of electrode materials different in work function, respectively, and the boundary surface between them is located below the upper surface of the fin.

公开(公告)号：US20180076206A1

公开(公告)日：2018-03-15

申请号：US15699756

申请日：2017-09-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi YOSHITOMI ,  Yoshiyuki KAWASHIMA

IPC: H01L27/1157 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L29/408 ,  H01L29/42344 ,  H01L29/4983 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

Abstract: The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A control gate electrode is formed over a semiconductor substrate via a first insulation film. A memory gate electrode is formed over the semiconductor substrate via a second insulation film having a charge accumulation part. The second insulation film is formed across between the semiconductor substrate and the memory gate electrode, and between the control gate electrode and the memory gate electrode. Between the control gate electrode and the memory gate electrode, a third insulation film is formed between the second insulation film and the memory gate electrode. The third insulation film is not formed under the memory gate electrode. A part of the memory gate electrode is present under the lower end face of the third insulation film.