公开(公告)号：US09997376B2

公开(公告)日：2018-06-12

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US09960054B2

公开(公告)日：2018-05-01

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US09942994B2

公开(公告)日：2018-04-10

申请号：US14750384

申请日：2015-06-25

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  Ulrik Riis Madsen ,  Donald Joseph Leahy

IPC: H01L23/552 ,  H05K3/40 ,  H01L23/498 ,  H05K1/11 ,  H05K9/00 ,  H05K3/30 ,  H01L21/56 ,  H01L23/00

CPC classification number: H05K3/4038 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/1461 ,  H05K1/115 ,  H05K3/301 ,  H05K9/0024 ,  H05K2201/0715 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.

公开(公告)号：US09929024B2

公开(公告)日：2018-03-27

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US09892937B2

公开(公告)日：2018-02-13

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US20160284570A1

公开(公告)日：2016-09-29

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/56 ,  H01L23/373 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/30604 ,  H01L2221/68381

Abstract: The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier, an etched flip chip die attached to a top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound having a high thermal conductivity improves thermal performance of the etched flip chip die.

Abstract translation: 本公开涉及具有增强的热性能的具有密封模具的半导体封装。 半导体封装包括载体，附着在载体的顶表面上的蚀刻倒装芯片模具，第一模具化合物和第二模具化合物。 蚀刻的倒装芯片芯片包括器件层，并且基本上不包括衬底。 第一模具化合物位于载体的顶表面上，围绕蚀刻的倒装芯片模具，并且延伸超过蚀刻的倒装芯片模具的顶表面，以形成空腔，蚀刻的倒装芯片裸片的顶表面露出 。 第二模具化合物填充空腔并与蚀刻的倒装芯片模具的顶表面接触。 具有高导热性的第二模具化合物改善了蚀刻的倒装芯片的热性能。

公开(公告)号：US20160284568A1

公开(公告)日：2016-09-29

申请号：US14959129

申请日：2015-12-04

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/30604 ,  H01L2221/68381

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract translation: 本公开涉及增强封装的倒装芯片的热性能。 根据示例性工艺，在载体的顶表面上附接多个倒装芯片管芯，并且在载体的顶表面上施加第一模具化合物以封装多个倒装芯片管芯。 将第一模具化合物减薄以暴露每个倒装芯片裸片的衬底，然后基本上蚀刻掉每个倒装芯片裸片的衬底，以提供在空腔底部具有暴露表面的蚀刻倒装芯片裸片。 接下来，施加具有高导热性的第二模具化合物以基本上填充每个空腔，并且第二模具化合物的顶表面被平坦化。 最后，封装的蚀刻倒装芯片芯片可以作为模块进行标记，分割和测试。

公开(公告)号：US20150296631A1

公开(公告)日：2015-10-15

申请号：US14750384

申请日：2015-06-25

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  Ulrik Riis Madsen ,  Donald Joseph Leahy

IPC: H05K3/40 ,  H05K9/00 ,  H05K3/30

CPC classification number: H05K3/4038 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/1461 ,  H05K1/115 ,  H05K3/301 ,  H05K9/0024 ,  H05K2201/0715 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.

Abstract translation: 在一个实施例中，具有用于两个或更多个模块的电路的元模块形成在衬底上，衬底优选为层压衬底。 最初在单个元模块上形成不同模块的电路。 每个模块将具有其中形成电路的一个或多个组件区域。 对于要屏蔽的每个部件区域，在基板上或基板上形成金属结构。 然后在元模块上的所有模块上形成单体，例如包覆模体。 至少与要被屏蔽的每个组件区域相关联的导电垂直互连访问结构（通孔）然后通过切割，钻孔或类似操作通过身体暴露。 接下来，将电磁屏蔽材料施加到待屏蔽的每个部件区域的主体的外表面并与暴露的导电通孔接触。