公开(公告)号：US20140106564A1

公开(公告)日：2014-04-17

申请号：US13850588

申请日：2013-03-26

Applicant: RF MICRO DEVICES, INC.

Inventor： John August Orlowski ,  David Jandzinski

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  H01L21/4832 ,  H01L23/49582 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.

Abstract translation: 选择性地电镀第一可镀层以形成一个或多个再分布路径。 IC封装的连接点连接到再分配路径，并且IC封装过度模制以确保稳定性。 然后去除第一耐热层，留下暴露的一个或多个再分布路径。 再分配路径允许IC封装的一个或多个接触点移动到新位置，以便于将IC封装集成到系统中。 通过从第一可镀层向上镀覆再分配路径，实现了不需要专门制造设备的精细几何形状，用于以最小的导体厚度重新定位IC封装的接触点。 因此，以低成本形成再分布层，同时最小化层对IC器件的操作的影响。

公开(公告)号：US10043707B2

公开(公告)日：2018-08-07

申请号：US13850588

申请日：2013-03-26

Applicant: RF Micro Devices, Inc.

Inventor： John August Orlowski ,  David Jandzinski

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/495 ,  H01L21/48

Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.

公开(公告)号：US09859132B2

公开(公告)日：2018-01-02

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US20140146489A1

公开(公告)日：2014-05-29

申请号：US13891809

申请日：2013-05-10

Applicant: RF Micro Devices, Inc.

Inventor： John August Orlowski ,  Donald Joseph Leahy ,  Thomas Scott Morris ,  David C. Dening ,  David Jandzinski

IPC: H05K1/02 ,  H05K3/38

CPC classification number: H05K3/3436 ,  H05K1/111 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/0338 ,  H05K2201/099 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic substrate includes a non-conductive body and one or more conductive features coupled to the non-conductive body. Each of the conductive features includes a base layer. To preserve the performance and conductivity of the one or more conductive features, each of the conductive features includes a protective layer formed over the base layer. The protective layer may include a first layer of silver formed over the base layer and a second layer of palladium formed over the first layer. By depositing the protective layer over the base layer of each of the conductive features, oxidation and exposure of the conductive features is prevented, or at least substantially reduced, since the first layer and the second layer provide a migration barrier for the metal in the base layer. However, the performance and conductivity of the conductive features are maintained due to the low resistivity of silver and palladium.

Abstract translation: 电子基板包括非导电体和耦合到非导电体的一个或多个导电特征。 每个导电特征包括基层。 为了保持一个或多个导电特征的性能和导电性，每个导电特征包括形成在基底层上的保护层。 保护层可以包括在基底层上形成的第一层银，以及形成在第一层上的第二层钯。 通过在每个导电特征的基底层上沉积保护层，防止或至少基本上减少了导电特征的氧化和曝光，因为第一层和第二层为基底中的金属提供迁移屏障 层。 然而，由于银和钯的低电阻率，导电特征的性能和导电性得以保持。

公开(公告)号：US09613831B2

公开(公告)日：2017-04-04

申请号：US14959129

申请日：2015-12-04

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/373

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/30604 ,  H01L2221/68381

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US09576822B2

公开(公告)日：2017-02-21

申请号：US14959129

申请日：2015-12-04

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/373

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US10020206B2

公开(公告)日：2018-07-10

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US09997376B2

公开(公告)日：2018-06-12

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US09960054B2

公开(公告)日：2018-05-01

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US09929024B2

公开(公告)日：2018-03-27

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.