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    SURFACE FINISH FOR CONDUCTIVE FEATURES ON SUBSTRATES
    1.
    发明申请
    SURFACE FINISH FOR CONDUCTIVE FEATURES ON SUBSTRATES 审中-公开
    表面导电性能的表面处理

    公开(公告)号：US20140146489A1

    公开(公告)日：2014-05-29

    申请号：US13891809

    申请日：2013-05-10

    Applicant: RF Micro Devices, Inc.

    Inventor： John August Orlowski ,  Donald Joseph Leahy ,  Thomas Scott Morris ,  David C. Dening ,  David Jandzinski

    IPC: H05K1/02 ,  H05K3/38

    CPC classification number: H05K3/3436 ,  H05K1/111 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/0338 ,  H05K2201/099 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613

    Abstract: An electronic substrate includes a non-conductive body and one or more conductive features coupled to the non-conductive body. Each of the conductive features includes a base layer. To preserve the performance and conductivity of the one or more conductive features, each of the conductive features includes a protective layer formed over the base layer. The protective layer may include a first layer of silver formed over the base layer and a second layer of palladium formed over the first layer. By depositing the protective layer over the base layer of each of the conductive features, oxidation and exposure of the conductive features is prevented, or at least substantially reduced, since the first layer and the second layer provide a migration barrier for the metal in the base layer. However, the performance and conductivity of the conductive features are maintained due to the low resistivity of silver and palladium.

    Abstract translation: 电子基板包括非导电体和耦合到非导电体的一个或多个导电特征。 每个导电特征包括基层。 为了保持一个或多个导电特征的性能和导电性，每个导电特征包括形成在基底层上的保护层。 保护层可以包括在基底层上形成的第一层银，以及形成在第一层上的第二层钯。 通过在每个导电特征的基底层上沉积保护层，防止或至少基本上减少了导电特征的氧化和曝光，因为第一层和第二层为基底中的金属提供迁移屏障 层。 然而，由于银和钯的低电阻率，导电特征的性能和导电性得以保持。

    Encapsulated dies with enhanced thermal performance
    2.
    发明授权
    Encapsulated dies with enhanced thermal performance 有权

    公开(公告)号：US09859132B2

    公开(公告)日：2018-01-02

    申请号：US15173037

    申请日：2016-06-03

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

    IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

    ELECTRONIC MODULES HAVING GROUNDED ELECTROMAGNETIC SHIELDS
    4.
    发明申请
    ELECTRONIC MODULES HAVING GROUNDED ELECTROMAGNETIC SHIELDS 有权
    具有接地电磁屏蔽的电子模块

    公开(公告)号：US20150124421A1

    公开(公告)日：2015-05-07

    申请号：US14595401

    申请日：2015-01-13

    Applicant: RF MICRO DEVICES, INC.

    Inventor： Donald Joseph Leahy ,  Brian D. Sawyer ,  Stephen Parker ,  Thomas Scott Morris

    IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

    CPC classification number: H05K1/0216 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/1461 ,  H05K1/0218 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/284 ,  H05K3/4614 ,  H05K2201/0715 ,  H05K2201/0949 ,  H05K2201/09618 ,  H05K2201/09709 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2924/00

    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.

    Abstract translation: 在一个实施例中，具有用于两个或更多个模块的电路的元模块形成在衬底上，衬底优选为层压衬底。 最初在单个元模块上形成不同模块的电路。 每个模块将具有其中形成电路的一个或多个组件区域。 对于要屏蔽的每个部件区域，在基板上或基板上形成金属结构。 然后在元模块上的所有模块上形成单体，例如包覆模体。 然后，通过切割，钻孔或类似的操作将待屏蔽的每个部件区域的金属结构的至少一部分暴露通过主体。 接下来，将电磁屏蔽材料施加到要被屏蔽并与金属结构的暴露部分接触的每个部件区域的主体的外表面上。

    Encapsulated dies with enhanced thermal performance
    6.
    发明授权
    Encapsulated dies with enhanced thermal performance 有权

    公开(公告)号：US09576822B2

    公开(公告)日：2017-02-21

    申请号：US14959129

    申请日：2015-12-04

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

    IPC: H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/373

    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

    Connection using conductive vias
    7.
    发明授权
    Connection using conductive vias 有权
    使用导电通孔连接

    公开(公告)号：US09420704B2

    公开(公告)日：2016-08-16

    申请号：US14447847

    申请日：2014-07-31

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  Ulrik Riis Madsen ,  Donald Joseph Leahy

    IPC: H01L23/58 ,  H05K3/40 ,  H01L23/498 ,  H01L23/552 ,  H05K1/11 ,  H05K9/00 ,  H05K3/30 ,  H01L21/56 ,  H01L23/00

    CPC classification number: H05K3/4038 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/1461 ,  H05K1/115 ,  H05K3/301 ,  H05K9/0024 ,  H05K2201/0715 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.

    Abstract translation: 在一个实施例中，具有用于两个或更多个模块的电路的元模块形成在衬底上，衬底优选为层压衬底。 最初在单个元模块上形成不同模块的电路。 每个模块将具有其中形成电路的一个或多个组件区域。 对于要屏蔽的每个部件区域，在基板上或基板上形成金属结构。 然后在元模块上的所有模块上形成单体，例如包覆模体。 至少与要被屏蔽的每个组件区域相关联的导电垂直互连访问结构（通孔）然后通过切割，钻孔或类似操作通过身体暴露。 接下来，将电磁屏蔽材料施加到待屏蔽的每个部件区域的主体的外表面并与暴露的导电通孔接触。

    CONNECTION USING CONDUCTIVE VIAS
    8.
    发明申请
    CONNECTION USING CONDUCTIVE VIAS 有权
    使用导电VIAS的连接

    公开(公告)号：US20140340859A1

    公开(公告)日：2014-11-20

    申请号：US14447847

    申请日：2014-07-31

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  Ulrik Riis Madsen ,  Donald Joseph Leahy

    IPC: H05K9/00 ,  H05K3/40 ,  H05K1/11

    CPC classification number: H05K3/4038 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/1461 ,  H05K1/115 ,  H05K3/301 ,  H05K9/0024 ,  H05K2201/0715 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.

    Abstract translation: 在一个实施例中，具有用于两个或更多个模块的电路的元模块形成在衬底上，衬底优选为层压衬底。 最初在单个元模块上形成不同模块的电路。 每个模块将具有其中形成电路的一个或多个组件区域。 对于要屏蔽的每个部件区域，在基板上或基板上形成金属结构。 然后在元模块上的所有模块上形成单体，例如包覆模体。 至少与要被屏蔽的每个组件区域相关联的导电垂直互连访问结构（通孔）然后通过切割，钻孔或类似操作通过身体暴露。 接下来，将电磁屏蔽材料施加到要屏蔽的每个部件区域的主体的外表面并与暴露的导电通孔接触。

    Encapsulated dies with enhanced thermal performance
    10.
    发明授权
    Encapsulated dies with enhanced thermal performance 有权

    公开(公告)号：US10020206B2

    公开(公告)日：2018-07-10

    申请号：US15173037

    申请日：2016-06-03

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

    IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

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