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公开(公告)号：US20140146489A1
公开(公告)日：2014-05-29
申请号：US13891809
申请日：2013-05-10
发明人： John August Orlowski , Donald Joseph Leahy , Thomas Scott Morris , David C. Dening , David Jandzinski
CPC分类号： H05K3/3436 , H05K1/111 , H05K3/244 , H05K3/3452 , H05K2201/0338 , H05K2201/099 , H05K2201/10674 , Y02P70/611 , Y02P70/613
摘要： An electronic substrate includes a non-conductive body and one or more conductive features coupled to the non-conductive body. Each of the conductive features includes a base layer. To preserve the performance and conductivity of the one or more conductive features, each of the conductive features includes a protective layer formed over the base layer. The protective layer may include a first layer of silver formed over the base layer and a second layer of palladium formed over the first layer. By depositing the protective layer over the base layer of each of the conductive features, oxidation and exposure of the conductive features is prevented, or at least substantially reduced, since the first layer and the second layer provide a migration barrier for the metal in the base layer. However, the performance and conductivity of the conductive features are maintained due to the low resistivity of silver and palladium.
摘要翻译： 电子基板包括非导电体和耦合到非导电体的一个或多个导电特征。 每个导电特征包括基层。 为了保持一个或多个导电特征的性能和导电性，每个导电特征包括形成在基底层上的保护层。 保护层可以包括在基底层上形成的第一层银，以及形成在第一层上的第二层钯。 通过在每个导电特征的基底层上沉积保护层，防止或至少基本上减少了导电特征的氧化和曝光，因为第一层和第二层为基底中的金属提供迁移屏障 层。 然而，由于银和钯的低电阻率，导电特征的性能和导电性得以保持。
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公开(公告)号：US09859132B2
公开(公告)日：2018-01-02
申请号：US15173037
申请日：2016-06-03
IPC分类号： H01L23/29 , H01L21/56 , H01L25/065 , H01L23/31 , H01L23/373 , H01L23/433 , H01L23/00
摘要： The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
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公开(公告)号：US09661739B2
公开(公告)日：2017-05-23
申请号：US14595401
申请日：2015-01-13
IPC分类号： H05K9/00 , H01L23/552 , H05K1/02 , H05K3/28 , H01L23/00 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/46
CPC分类号： H05K1/0216 , H01L23/552 , H01L24/97 , H01L2924/1461 , H05K1/0218 , H05K1/115 , H05K1/181 , H05K3/0052 , H05K3/0097 , H05K3/284 , H05K3/4614 , H05K2201/0715 , H05K2201/0949 , H05K2201/09618 , H05K2201/09709 , Y10T29/49124 , Y10T29/4913 , Y10T29/49146 , Y10T29/49171 , H01L2924/00
摘要： In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.
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公开(公告)号：US20150124421A1
公开(公告)日：2015-05-07
申请号：US14595401
申请日：2015-01-13
CPC分类号： H05K1/0216 , H01L23/552 , H01L24/97 , H01L2924/1461 , H05K1/0218 , H05K1/115 , H05K1/181 , H05K3/0052 , H05K3/0097 , H05K3/284 , H05K3/4614 , H05K2201/0715 , H05K2201/0949 , H05K2201/09618 , H05K2201/09709 , Y10T29/49124 , Y10T29/4913 , Y10T29/49146 , Y10T29/49171 , H01L2924/00
摘要： In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.
摘要翻译： 在一个实施例中，具有用于两个或更多个模块的电路的元模块形成在衬底上，衬底优选为层压衬底。 最初在单个元模块上形成不同模块的电路。 每个模块将具有其中形成电路的一个或多个组件区域。 对于要屏蔽的每个部件区域，在基板上或基板上形成金属结构。 然后在元模块上的所有模块上形成单体，例如包覆模体。 然后，通过切割，钻孔或类似的操作将待屏蔽的每个部件区域的金属结构的至少一部分暴露通过主体。 接下来，将电磁屏蔽材料施加到要被屏蔽并与金属结构的暴露部分接触的每个部件区域的主体的外表面上。
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公开(公告)号：US09613831B2
公开(公告)日：2017-04-04
申请号：US14959129
申请日：2015-12-04
IPC分类号： H01L21/50 , H01L21/56 , H01L25/065 , H01L23/31 , H01L23/29 , H01L23/373
CPC分类号： H01L21/563 , H01L21/561 , H01L21/568 , H01L23/29 , H01L23/3135 , H01L23/373 , H01L23/3737 , H01L23/4334 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0655 , H01L2224/10 , H01L2224/131 , H01L2224/16227 , H01L2224/81 , H01L2224/81801 , H01L2224/92 , H01L2224/97 , H01L2924/15311 , H01L2924/15313 , H01L2924/014 , H01L2924/00014 , H01L21/56 , H01L2221/68304 , H01L21/304 , H01L21/30604 , H01L2221/68381
摘要： The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
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公开(公告)号：US09576822B2
公开(公告)日：2017-02-21
申请号：US14959129
申请日：2015-12-04
IPC分类号： H01L21/50 , H01L21/56 , H01L25/065 , H01L23/31 , H01L23/29 , H01L23/373
摘要： The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
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公开(公告)号：US09420704B2
公开(公告)日：2016-08-16
申请号：US14447847
申请日：2014-07-31
IPC分类号： H01L23/58 , H05K3/40 , H01L23/498 , H01L23/552 , H05K1/11 , H05K9/00 , H05K3/30 , H01L21/56 , H01L23/00
CPC分类号： H05K3/4038 , H01L21/561 , H01L23/49827 , H01L23/552 , H01L24/97 , H01L2924/1461 , H05K1/115 , H05K3/301 , H05K9/0024 , H05K2201/0715 , Y10T29/49165 , H01L2924/00
摘要： In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.
摘要翻译： 在一个实施例中，具有用于两个或更多个模块的电路的元模块形成在衬底上，衬底优选为层压衬底。 最初在单个元模块上形成不同模块的电路。 每个模块将具有其中形成电路的一个或多个组件区域。 对于要屏蔽的每个部件区域，在基板上或基板上形成金属结构。 然后在元模块上的所有模块上形成单体，例如包覆模体。 至少与要被屏蔽的每个组件区域相关联的导电垂直互连访问结构（通孔）然后通过切割，钻孔或类似操作通过身体暴露。 接下来，将电磁屏蔽材料施加到待屏蔽的每个部件区域的主体的外表面并与暴露的导电通孔接触。
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公开(公告)号：US20140340859A1
公开(公告)日：2014-11-20
申请号：US14447847
申请日：2014-07-31
CPC分类号： H05K3/4038 , H01L21/561 , H01L23/49827 , H01L23/552 , H01L24/97 , H01L2924/1461 , H05K1/115 , H05K3/301 , H05K9/0024 , H05K2201/0715 , Y10T29/49165 , H01L2924/00
摘要： In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.
摘要翻译： 在一个实施例中，具有用于两个或更多个模块的电路的元模块形成在衬底上，衬底优选为层压衬底。 最初在单个元模块上形成不同模块的电路。 每个模块将具有其中形成电路的一个或多个组件区域。 对于要屏蔽的每个部件区域，在基板上或基板上形成金属结构。 然后在元模块上的所有模块上形成单体，例如包覆模体。 至少与要被屏蔽的每个组件区域相关联的导电垂直互连访问结构（通孔）然后通过切割，钻孔或类似操作通过身体暴露。 接下来，将电磁屏蔽材料施加到要屏蔽的每个部件区域的主体的外表面并与暴露的导电通孔接触。
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9.发明申请USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE 审中-公开通过一个半导体芯片的钝化层使用互连保护公开(公告)号：US20140021603A1
公开(公告)日：2014-01-23
申请号：US13948516
申请日：2013-07-23
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L24/14 , H01L21/76885 , H01L23/3192 , H01L23/367 , H01L23/4824 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L2224/02206 , H01L2224/02215 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05166 , H01L2224/05548 , H01L2224/05552 , H01L2224/05567 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/13013 , H01L2224/13022 , H01L2224/13024 , H01L2224/13026 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/14519 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/05442 , H01L2924/10329 , H01L2924/1305 , H01L2924/13051 , H01L2924/01047 , H01L2924/00
摘要： A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.
摘要翻译： 公开了一种包括第一半导体器件，第一钝化层和第一互连凸点的半导体管芯。 第一钝化层在第一半导体器件之上，其包括第一组器件指状物。 第一互连凸块被热电连接到第一组设备手指中的每一个。 另外，第一互连凸块突出穿过第一钝化层中的第一开口。
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公开(公告)号：US10020206B2
公开(公告)日：2018-07-10
申请号：US15173037
申请日：2016-06-03
IPC分类号： H01L23/29 , H01L21/56 , H01L25/065 , H01L23/31 , H01L23/373 , H01L23/433 , H01L23/00
摘要： The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
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