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    System and method for enhancing the speed of dynamic timing simulation using delay assessment at compile time
    11.
    发明授权
    System and method for enhancing the speed of dynamic timing simulation using delay assessment at compile time 有权
    在编译时使用延迟评估来提高动态时序仿真的速度的系统和方法

    公开(公告)号：US07047175B1

    公开(公告)日：2006-05-16

    申请号：US10015180

    申请日：2001-11-16

    申请人： Manish Jain ,  Badri P. Gopalan

    发明人： Manish Jain ,  Badri P. Gopalan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method and system for reducing the time required for execution of the dynamic timing simulation for a logic simulator. For a logic circuit simulator having a compilation phase and a runtime phase, a delay assessment is performed during the compilation phase in order to identify storage elements that are exempt from possible timing violations at runtime. The runtime timing checks are removed from the exempt storage elements, thereby reducing the runtime calculation effort. Additionally, combinational portions of the circuit that drive the exempt storage elements are examined for element delays that can be effectively eliminated (e.g., zero delayed) from the runtime calculations, thereby providing a further reduction in the computational overhead via the use of cycle based simulation for these.

    摘要翻译： 一种用于减少执行逻辑模拟器的动态定时仿真所需的时间的方法和系统。 对于具有编译阶段和运行时阶段的逻辑电路模拟器，在编译阶段期间执行延迟评估，以便识别在运行时免除可能的定时违反的存储元件。 运行时定时检查从免除存储元件中移除，从而减少运行时计算工作。 此外，驱动免除存储元件的电路的组合部分被检查可以从运行时计算中有效地消除（例如，零延迟）的元件延迟，从而通过使用基于循环的仿真进一步减少计算开销 对于这些。

    Data communication with compensation for packet loss
    13.
    发明授权
    Data communication with compensation for packet loss 有权
    数据通信与丢包补偿

    公开(公告)号：US09237105B2

    公开(公告)日：2016-01-12

    申请号：US12632834

    申请日：2009-12-08

    申请人： Cheng Huang ,  Manish Jain ,  Jin Li ,  Amit Kumar Mondal ,  Aleksandar Kuzmanovic

    发明人： Cheng Huang ,  Manish Jain ,  Jin Li ,  Amit Kumar Mondal ,  Aleksandar Kuzmanovic

    IPC分类号： H04L12/801 ,  H04L1/00 ,  H04L1/08 ,  H04L12/853 ,  H04L12/825 ,  H04L12/811

    CPC分类号： H04L47/14 ,  H04L1/0009 ,  H04L1/0018 ,  H04L1/0057 ,  H04L1/08 ,  H04L47/2416 ,  H04L47/26 ,  H04L47/38 ,  H04L2001/0097

    摘要： Described is a technology by which a relay is coupled (e.g., by a wire) to a network and (e.g., by a wireless link) to an endpoint. Incoming data packets directed towards the endpoint are processed by the relay according to an error correction scheme, such as one that replicates packets. The reprocessed packets, which in general are more robust against packet loss, are then sent to the endpoint. For outgoing data packets received from the endpoint, the relay reprocesses the outgoing packets based upon the error correction scheme, such as to remove redundant packets before transmitting them to the network over the wire. Also described are various error correction schemes, and various types of computing devices that may be used as relays. The relay may be built into the network infrastructure, and/or a directory service may be employed to automatically find a suitable relay node for an endpoint device.

    摘要翻译： 描述了一种技术，通过该技术将中继器（例如，通过有线）耦合到网络，并且（例如，通过无线链路）耦合到端点。 根据诸如复制分组的错误校正方案，继电器处理针对端点的进入数据分组。 然后将再处理的数据包（通常对数据包丢失更加鲁棒）发送到端点。 对于从端点接收到的输出数据分组，中继器基于纠错方案重新处理输出分组，例如在通过线路将其发送到网络之前去除冗余分组。 还描述了各种错误校正方案以及可以用作中继的各种类型的计算设备。 可以将中继器内置到网络基础设施中，和/或可以采用目录服务来自动地为端点设备找到合适的中继节点。

    Method and apparatus for executing a hardware simulation and verification solution
    15.
    发明授权
    Method and apparatus for executing a hardware simulation and verification solution 有权
    用于执行硬件仿真和验证解决方案的方法和装置

    公开(公告)号：US08121825B2

    公开(公告)日：2012-02-21

    申请号：US12112222

    申请日：2008-04-30

    申请人： Manish Jain ,  Subha S. Chowdhury ,  Sridhar Seshadri

    发明人： Manish Jain ,  Subha S. Chowdhury ,  Sridhar Seshadri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5022

    摘要： One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

    摘要翻译： 本发明的一个实施例提供了在多处理器系统上执行硬件仿真和验证解决方案的系统和技术。 硬件仿真和验证解决方案可以划分成不同的模块，其中可以包括模拟内核来模拟信号值的变化，值改变转储模块，用于将信号值的变化存储在计算机可读存储介质上，功能覆盖模块 检查功能，切换覆盖模块以检查信号切换，用于检查复杂行为的断言引擎，以及测试台模块来生成测试场景。 本发明的实施例可以在不同的处理器上执行不同的模块，从而提高性能。

    Process for Audible Acoustic Frequency Management in Gas Flow Systems
    17.
    发明申请
    Process for Audible Acoustic Frequency Management in Gas Flow Systems 审中-公开
    气体流量系统声音频率管理过程

    公开(公告)号：US20110005859A1

    公开(公告)日：2011-01-13

    申请号：US12920398

    申请日：2009-02-27

    申请人： Ali Berker ,  Manish Jain ,  Smarajit Mitra ,  Sanat Mohanty

    发明人： Ali Berker ,  Manish Jain ,  Smarajit Mitra ,  Sanat Mohanty

    IPC分类号： F01N1/24 ,  E04F17/04

    CPC分类号： G10K11/172 ,  F24F13/0263 ,  F24F13/24 ,  F24F2013/245

    摘要： A sound insulation process comprises (a) providing at least one sound barrier comprising a substantially periodic array of structures disposed in a first medium having a first density, the array comprising at least one row of at least two of the structures, the structures being made of a second medium having a second density that is greater than the first density, the second medium being a viscoelastic medium, an elastic medium, or a combination thereof, and the first medium being a gaseous medium; and (b) placing the at least one sound barrier in at least one at least partially enclosed gas stream in a manner such that the row of structures extends in a direction that is perpendicular to the direction of flow of the gas stream.

    摘要翻译： 隔音过程包括（a）提供至少一个声屏障，包括设置在具有第一密度的第一介质中的基本上周期性的阵列阵列，所述阵列包括至少一排至少两排结构，所述结构被制成 具有大于第一密度的第二密度的第二介质，第二介质是粘弹性介质，弹性介质或其组合，第一介质是气态介质; 和（b）将所述至少一个声屏障放置在至少一个至少部分封闭的气流中，使得所述一排结构沿垂直于所述气流的流动方向的方向延伸。

    Monofilaments to offset curl in warp bound forming fabrics
    18.
    发明授权
    Monofilaments to offset curl in warp bound forming fabrics 有权
    用于抵消经向成形织物中的卷曲的单丝

    公开(公告)号：US07631669B2

    公开(公告)日：2009-12-15

    申请号：US11439676

    申请日：2006-05-24

    申请人： David S. Rougvie ,  Hayward Bradford Arthur ,  Louis Jay Jandris ,  Manish Jain

    发明人： David S. Rougvie ,  Hayward Bradford Arthur ,  Louis Jay Jandris ,  Manish Jain

    IPC分类号： D21F1/10 ,  D21F7/08 ,  D03D3/04 ,  D03D25/00

    CPC分类号： D21F1/0027 ,  D21F1/0045

    摘要： A papermaking fabric having a top layer and a bottom layer of interwoven machine direction (MD) yarns and cross-machine direction (CD) yarns bound together with warp binder yarns. At least some of the CD yarns are made of a material which generates a strong contractive force when returned to room temperature after heat-setting (annealing under MD tension). These CD yarns are positioned such that the strong contractive force offsets tension forces generated when the fabric is placed under load and which typically result in an edge curl. An exemplary material for these CD yarns is polybutylene terephthalate (PBT).

    摘要翻译： 一种造纸织物，其具有与经向粘合剂纱线结合在一起的交织机器方向（MD）纱线和横向（CD）纱线的顶层和底层。 至少一些CD纱由在热定形（MD张力退火）之后返回到室温时产生强收缩力的材料制成。 这些CD纱定位成使得强的收缩力抵消当织物放置在负载下时产生的张力，并且通常导致边缘卷曲。 这些CD纱线的示例性材料是聚对苯二甲酸丁二醇酯（PBT）。

    Voltage regulator operable over a wide range of supply voltage
    19.
    发明授权
    Voltage regulator operable over a wide range of supply voltage 有权
    电压调节器可在宽范围的电源电压下工作

    公开(公告)号：US06963460B2

    公开(公告)日：2005-11-08

    申请号：US10295263

    申请日：2002-11-14

    申请人： Manish Jain ,  Roberto Alini

    发明人： Manish Jain ,  Roberto Alini

    IPC分类号： G11B20/10 ,  G05F1/10 ,  G11B5/02 ,  G11B5/09 ,  G11B19/00

    CPC分类号： G11B19/00 ,  G11B19/2063

    摘要： A voltage regulator includes an output node and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.

    摘要翻译： 电压调节器包括输出节点和第一和第二调节器电路。 当电源电压等于或超过预定阈值时，第一调节器电路在输出节点上产生第一调节电压，并且当电源电压小于预定阈值时，第二调节器电路在输出节点上产生第二调节电压。