公开(公告)号：US09972369B2

公开(公告)日：2018-05-15

申请号：US14923345

申请日：2015-10-26

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  David Wang

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C7/10 ,  G06F11/07 ,  G11C29/04 ,  G11C5/04

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US10185499B1

公开(公告)日：2019-01-22

申请号：US14536312

申请日：2014-11-07

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F3/06

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

公开(公告)号：US12204758B2

公开(公告)日：2025-01-21

申请号：US18235068

申请日：2023-08-17

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F3/06 ,  G06F13/00 ,  G06F13/16

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

公开(公告)号：US11733870B2

公开(公告)日：2023-08-22

申请号：US16249109

申请日：2019-01-16

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/00 ,  G06F13/1642

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

公开(公告)号：US10983700B2

公开(公告)日：2021-04-20

申请号：US16831130

申请日：2020-03-26

Applicant: Rambus Inc.

Inventor： David Wang

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/00

Abstract: In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.