-
公开(公告)号：US10211841B2
公开(公告)日：2019-02-19
申请号：US15667184
申请日：2017-08-02
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/00 , H03K5/156 , G11C7/10 , H03L7/091 , G11C7/22 , H04L7/00 , H04L7/033 , H03L7/08 , H03L7/099 , G11C7/04
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
-
Patent Agency Ranking
公开(公告)号：US20170351282A1
公开(公告)日：2017-12-07
申请号：US15626096
申请日：2017-06-17
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
-
公开(公告)号：US08942309B1
公开(公告)日：2015-01-27
申请号：US13863243
申请日：2013-04-15
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Wilson
CPC classification number: H04L25/14
Abstract: An intermediate voltage is maintained between a first voltage and a second voltage by conditionally or selectively performing data bus inversion (DBI) and/or data swap operations on a first and second transmit channel. The operations are performed to, in some instances, create a current imbalance between the first and second channel where the intermediate voltage drifts toward a target range or target value between the first voltage and second voltage in response to the created imbalance.
Abstract translation: 通过在第一和第二发射信道上有条件地或有选择地执行数据总线反相（DBI）和/或数据交换操作来将中间电压保持在第一电压和第二电压之间。 执行这些操作以在一些情况下产生第一和第二通道之间的电流不平衡，其中中间电压响应于所产生的不平衡而偏移到目标范围或第一电压和第二电压之间的目标值。
-
14.发明申请公开(公告)号：US20130346822A1
公开(公告)日：2013-12-26
申请号：US13914091
申请日：2013-06-10
Applicant: Rambus Inc.
Inventor： Jade M. Kizer , John Wilson , Lei Luo , Frederick A. Ware , Jared L. Zerbe
IPC: H03M13/47
CPC classification number: H03M13/47 , H04L25/4919
Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
Abstract translation: 描述电路的实施例。 在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。 此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。 此外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡以及M个符号集合中的第二值的实例的数量，并且如果不平衡是 检测到，这会导致错误条件。
-
公开(公告)号：US10067519B2
公开(公告)日：2018-09-04
申请号：US15626096
申请日：2017-06-17
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
-
公开(公告)号：US20180083642A1
公开(公告)日：2018-03-22
申请号：US15667184
申请日：2017-08-02
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
CPC classification number: H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K5/1565 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
-
-
-
-
-
Search Results
16
records
(took 0.028 seconds)
