公开(公告)号：US10211841B2

公开(公告)日：2019-02-19

申请号：US15667184

申请日：2017-08-02

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/00 ,  H03K5/156 ,  G11C7/10 ,  H03L7/091 ,  G11C7/22 ,  H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03L7/099 ,  G11C7/04

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US20190086990A1

公开(公告)日：2019-03-21

申请号：US16134577

申请日：2018-09-18

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

IPC: G06F1/32 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

公开(公告)号：US20180083642A1

公开(公告)日：2018-03-22

申请号：US15667184

申请日：2017-08-02

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/091 ,  H03L7/08 ,  H03L7/099

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US20240168873A1

公开(公告)日：2024-05-23

申请号：US18162824

申请日：2021-08-06

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Barry William Daly ,  Thomas J. Giovannini ,  Lei Luo ,  Masum Hossain

IPC: G06F12/02 ,  G11C11/408

CPC classification number: G06F12/0223 ,  G11C11/4082

Abstract: Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.

公开(公告)号：US10541693B2

公开(公告)日：2020-01-21

申请号：US16242475

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/091 ,  H03K5/156 ,  H03L7/00 ,  G11C7/10 ,  G11C7/22 ,  H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03L7/099 ,  G11C7/04

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US09748960B2

公开(公告)日：2017-08-29

申请号：US14456716

申请日：2014-08-11

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/091 ,  H03L7/099 ,  H03L7/00 ,  G11C7/10 ,  G11C7/22 ,  H04L7/033 ,  H03L7/08 ,  H04L7/00 ,  G11C7/04

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US20150177815A1

公开(公告)日：2015-06-25

申请号：US14416088

申请日：2013-09-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a START memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract translation: 所公开的实施例涉及支持动态突发以促进START存储器控制器和存储设备之间的频率敏捷通信的系统。 在操作期间，系统监视在存储器件和存储器控制器之间的接口处接收到的参考时钟信号。 在检测到从全速率到子速率的参考时钟信号中的频率变化时，接口以突发模式操作，其中数据通过由接口的部分断电的中间的低功率间隔分开的脉冲串传送。

公开(公告)号：US20250036187A1

公开(公告)日：2025-01-30

申请号：US18795900

申请日：2024-08-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

IPC: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/16 ,  G06F13/28

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

公开(公告)号：US12086010B2

公开(公告)日：2024-09-10

申请号：US17891768

申请日：2022-08-19

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

IPC: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  Y02D10/00 ,  Y02D30/50

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

公开(公告)号：US20210064116A1

公开(公告)日：2021-03-04

申请号：US17002269

申请日：2020-08-25

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

IPC: G06F1/3237 ,  G06F13/16 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/28

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.