公开(公告)号：US20210096616A1

公开(公告)日：2021-04-01

申请号：US16634531

申请日：2018-07-23

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  John Eric LINSTADT ,  Thomas VOGELSANG

IPC: G06F1/20 ,  H05K7/20 ,  H01L23/367

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain.

公开(公告)号：US20200335150A1

公开(公告)日：2020-10-22

申请号：US16838646

申请日：2020-04-02

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  John Eric LINSTADT ,  Liji GOPALAKRISHNAN

IPC: G11C11/408 ,  G06F13/42 ,  G11C11/4091 ,  G11C11/4094

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

公开(公告)号：US20160379710A1

公开(公告)日：2016-12-29

申请号：US15039784

申请日：2014-12-04

Applicant: RAMBUS INC.

Inventor： Deepak Chandra SEKAR ,  Wayne Frederick ELLIS ,  Brent Steven HAUKNESS ,  Gary Bela BRONNER ,  Thomas VOGELSANG

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C7/08 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract translation: 存储器件包括多个电阻存储器单元和多个字线。 每个电阻性存储单元包括电阻性存储器元件，与电阻性存储元件串联电耦合的第一开关元件，以及与第一开关元件串联电耦合的第二开关元件。 每个电阻存储单元中的第一开关元件和第二开关元件耦合到不同的字线。

公开(公告)号：US20240385974A1

公开(公告)日：2024-11-21

申请号：US18669049

申请日：2024-05-20

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Craig E. HAMPEL

IPC: G06F13/16 ,  G06F7/483

Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

公开(公告)号：US20240203474A1

公开(公告)日：2024-06-20

申请号：US17909940

申请日：2021-03-08

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Brent S. HAUKNESS

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/40611 ,  G11C11/40626 ,  G11C11/4091 ,  G11C11/4094

Abstract: The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.

公开(公告)号：US20240119995A1

公开(公告)日：2024-04-11

申请号：US18489275

申请日：2023-10-18

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4085

Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.

公开(公告)号：US20220229601A1

公开(公告)日：2022-07-21

申请号：US17576529

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Michael Raymond MILLER ,  Steven C. WOO

IPC: G06F3/06 ,  G11C7/10

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.

公开(公告)号：US20220138125A1

公开(公告)日：2022-05-05

申请号：US17504739

申请日：2021-10-19

Applicant: Rambus Inc.

Inventor： Steven C. WOO ,  Thomas VOGELSANG ,  Joseph James TRINGALI ,  Pooneh SAFAYENIKOO

IPC: G06F13/16 ,  H01L25/18 ,  H01L25/065

Abstract: Processing elements include interfaces that allow direct access to memory banks on one or more DRAMs in an integrated circuit stack. These additional (e.g., per processing element) direct interfaces may allow the processing elements to have direct access to the data in the DRAM stack. Based on the size/type of operands being processed, and the memory bandwidth of the direct interfaces, rate calculation circuitry on the processor die determines the speed each processing element and/or processing nodes within each processing element are operated.

公开(公告)号：US20210407579A1

公开(公告)日：2021-12-30

申请号：US17295753

申请日：2019-11-26

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.

公开(公告)号：US20250045197A1

公开(公告)日：2025-02-06

申请号：US18775487

申请日：2024-07-17

Applicant: Rambus Inc.

Inventor： John Eric LINSTADT ,  Thomas VOGELSANG

IPC: G06F12/02

Abstract: A memory device includes functionality (e.g., mode, command, etc.) to concurrently activate/access a plurality of rows across a corresponding plurality of memory banks. When concurrently accessing the memory banks, the row address and column address are provided to all of the memory banks being accessed. Multiplexer/demultiplexer (e.g., steering logic) may be used to route non-payload (e.g., metadata) from the concurrently activated memory banks to/from the data interface of the memory device. The steering logic may route and/or serialize the metadata from the concurrently activated memory banks of the bank group such that the non-payload data from a respective memory bank is communicated via the same data signal(s) (e.g., DQ[0], DQ[1], etc.) of the data interface.