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    Synchronous wired-OR ACK status for memory with variable write latency
    11.
    发明授权
    Synchronous wired-OR ACK status for memory with variable write latency 有权

    公开(公告)号：US10468544B2

    公开(公告)日：2019-11-05

    申请号：US15369244

    申请日：2016-12-05

    Applicant: Rambus Inc.

    Inventor： Yohan Frans ,  Simon Li ,  Eric Linstadt ,  Jun Kim

    IPC: G06F12/02 ,  H01L31/0236 ,  G06F13/16 ,  G06F3/06 ,  G06F13/372 ,  G06F12/00

    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

    MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE
    14.
    发明公开
    MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE 审中-公开

    公开(公告)号：US20230395103A1

    公开(公告)日：2023-12-07

    申请号：US18195860

    申请日：2023-05-10

    Applicant: Rambus Inc.

    Inventor： Yohan Frans

    IPC: G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22

    CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657

    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

    MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE
    15.
    发明申请
    MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE 有权

    公开(公告)号：US20210217448A1

    公开(公告)日：2021-07-15

    申请号：US17135174

    申请日：2020-12-28

    Applicant: Rambus Inc.

    Inventor： Yohan Frans

    IPC: G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22

    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

    Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die
    16.
    发明授权
    Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die 有权

    公开(公告)号：US10885949B2

    公开(公告)日：2021-01-05

    申请号：US16653252

    申请日：2019-10-15

    Applicant: Rambus Inc.

    Inventor： Yohan Frans

    IPC: G11C8/18 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  H01L25/065

    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

    Synchronous wired-or ACK status for memory with variable write latency
    20.
    发明授权
    Synchronous wired-or ACK status for memory with variable write latency 有权
    具有可变写延迟的存储器的同步有线或ACK状态

    公开(公告)号：US09515204B2

    公开(公告)日：2016-12-06

    申请号：US13804334

    申请日：2013-03-14

    Applicant: Rambus Inc.

    Inventor： Yohan Frans ,  Simon Li ,  Eric Lindstadt ,  Jun Kim

    IPC: G06F12/02 ,  H01L31/0236 ,  G06F12/00 ,  G06F13/16

    CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1684 ,  G06F13/372 ,  Y02D10/14

    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

    Abstract translation: 存储器控制器包括用于将存储器命令发送到与存储器控制器相关联的多个存储器件的命令接口。 存储器控制器还包括确认界面，用于通过耦合在存储器控制器和多个存储器件之间的共享确认链路从多个存储器设备接收确认状态分组，该确认状态分组指示该命令是否被多个 的存储器件。 此外，存储器控制器包括存储器控制器核心，用于对确认状态分组进行解码，以识别对应于多个存储器设备中的每一个的确认状态分组的一部分。

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