公开(公告)号：US08122222B2

公开(公告)日：2012-02-21

申请号：US12105360

申请日：2008-04-18

Applicant: Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F12/0862 ,  G06F12/0215 ,  G06F12/0831 ,  G06F2212/1041 ,  G06F2212/507 ,  G06F2212/6022 ,  G06F2212/6024

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.

Abstract translation: 访问推测预测器可以基于范围预测器是否预测本地或全局请求是否需要以获得数据请求的数据来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，可以从第一数据请求中提取第一地址和范围预测器。 可以确定接收第一数据请求的存储器控​​制器是否是本地的第一数据请求的源。 可以基于存储器控制器是否为第一数据请求的源的本地来控制来自主存储器的用于第一数据请求的数据的推测性检索，以及范围预测器是否预测本地或全局请求是否被预测为 必要。

公开(公告)号：US07836257B2

公开(公告)日：2010-11-16

申请号：US11959804

申请日：2007-12-19

Applicant: Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

Inventor： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

IPC: G06F12/00

CPC classification number: G06F12/127 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/128

Abstract: A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

Abstract translation: 用于管理高速缓存的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作。 第一PU确定第一PU的第一高速缓存中的多条高速缓存线之一必须被第一数据块替换，并且确定第一数据块是否是来自多个PU中的另一个的受害缓存行。 在第一数据块不是来自多个PU中的另一个的第一数据块的情况下，第一高速缓存不包含一致性状态的高速缓存行无效，并且第一高速缓存包含移动的一致性状态的高速缓存行， 第一PU选择移动的一致性状态的高速缓存行，将第一数据块存储在所选择的高速缓存行中，并更新第一数据块的一致性状态。

公开(公告)号：US07603490B2

公开(公告)日：2009-10-13

申请号：US11621776

申请日：2007-01-10

Applicant: Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

Inventor： Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

IPC: G06F13/28 ,  G06F13/32

CPC classification number: G06F13/28

Abstract: A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.

Abstract translation: 直接存储器访问（DMA）设备包括屏障和中断机制，允许中断和邮箱操作以确保正确操作的方式发生，但仍然允许在可能的情况下发生高性能无序数据移动。 某些描述符被定义为“屏障描述符”。 当DMA设备遇到屏障描述符时，它确保所有先前的描述符在屏障描述符完成之前完成。 DMA设备进一步确保在与屏障描述符关联的数据移动完成之前，屏障描述符产生的任何中断都不会断言。 DMA控制器仅允许由屏障描述符生成中断。 屏障描述符概念还允许软件将邮箱完成消息嵌入到描述符的分散/收集链接列表中。

公开(公告)号：US20090164735A1

公开(公告)日：2009-06-25

申请号：US11959793

申请日：2007-12-19

Applicant: Richard Nicholas ,  Jason Alan Cox ,  Robert John Dorsey ,  Hien Minh Le ,  Eric Francis Robinson ,  Thuong Quang Truong

Inventor： Richard Nicholas ,  Jason Alan Cox ,  Robert John Dorsey ,  Hien Minh Le ,  Eric Francis Robinson ,  Thuong Quang Truong

IPC: G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084

Abstract: A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

Abstract translation: 用于维持高速缓存一致性的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有高速缓存，并且每个PU耦合到多个PU中的至少另一个。 第一PU接收用于存储在第一PU的第一高速缓存中的第一数据块。 第一个PU将第一个数据块存储在第一个缓存中。 第一PU将第一相关性状态和第一标签分配给第一数据块，其中第一相关性状态是指示第一PU是否已经访问了第一数据块的多个相关性状态之一。 多个相关性状态还指示在第一PU未访问第一数据块的情况下，第一PU从相邻PU接收到第一数据块。

公开(公告)号：US20090113097A1

公开(公告)日：2009-04-30

申请号：US11927911

申请日：2007-10-30

Applicant: Bernard Charles Drerup ,  Richard Nicholas ,  Prasanna Srinivasan

Inventor： Bernard Charles Drerup ,  Richard Nicholas ,  Prasanna Srinivasan

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: In a method and apparatus associated with a bus controller, a set of mechanisms are selectively added to the bus controller, as well as to slave devices connected to the bus controller. A mechanism is also added to one or more master devices connected to the bus controller, in order to provide the master devices with a transaction ordering capability. The added mechanisms collectively achieve the objective of supporting connection of multiple slave devices to a common controller interface, and at the same time allowing pipelined operation of the slave devices. One embodiment of the invention is directed to a method for use with a bus and an associated bus controller, wherein the bus controller has respective master and slave interfaces for use in selectively interconnecting master devices and slave devices. The method comprises the steps of connecting one or more of the master devices to one of the master interfaces, and connecting each of a plurality of slave devices to the same one of the slave interfaces. The method further comprises operating a connected master device to send multiple commands to a selected one of the connected slave devices in accordance with a command pipelining procedure.

Abstract translation: 在与总线控制器相关联的方法和装置中，一组机制被选择性地添加到总线控制器以及连接到总线控制器的从设备。 为了向主设备提供事务排序能力，还将一种机制添加到连接到总线控制器的一个或多个主设备中。 所附加的机制共同实现支持多个从设备连接到公共控制器接口的目的，并且同时允许从设备的流水线操作。 本发明的一个实施例涉及一种与总线和相关联的总线控制器一起使用的方法，其中总线控制器具有用于选择性地互连主设备和从设备的主和从接口。 该方法包括以下步骤：将一个或多个主设备连接到一个主接口，并将多个从设备中的每一个连接到同一个从接口。 该方法还包括操作连接的主设备，以根据命令流水线过程向连接的从设备中的所选一个发送多个命令。

公开(公告)号：US20090106466A1

公开(公告)日：2009-04-23

申请号：US12112818

申请日：2008-04-30

Applicant: BERNARD C. DRERUP ,  Richard Nicholas

Inventor： BERNARD C. DRERUP ,  Richard Nicholas

IPC: G06F13/372

CPC classification number: G06F13/364

Abstract: A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract translation: 公开了一种用于在单个数据总线上搭载多个数据期限以实现更高总线利用率的设计结构。 在设计结构的一个实施例中，计算机辅助设计系统中的一种方法包括发送对总线许可的请求的源设备，以向连接源设备和目的地设备的数据总线传送数据。 设备接收总线许可，并且设备内的逻辑确定分配给总线授权的数据总线的带宽是否将被数据填充。 如果分配给总线授权的数据总线的带宽不会被数据填充，则设备将附加数据附加到第一个数据，并在第一个数据的总线授权期间将组合的数据传送到数据总线。 当分配给总线授权的数据总线的带宽将由第一个数据填充时，设备在总线授权期间只将第一个数据传送到数据总线。

公开(公告)号：US20090106465A1

公开(公告)日：2009-04-23

申请号：US11877296

申请日：2007-10-23

Applicant: Bernard C. Drerup ,  Richard Nicholas

Inventor： Bernard C. Drerup ,  Richard Nicholas

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract translation: 提出了一种改进的方法，设备和数据处理系统。 在一个实施例中，该方法包括发送对总线许可的请求的源设备，以向连接源设备和目的地设备的数据总线传送数据。 设备接收总线许可，并且设备内的逻辑确定分配给总线授权的数据总线的带宽是否将被数据填充。 如果分配给总线授权的数据总线的带宽不会被数据填充，则设备将附加数据附加到第一个数据，并在第一个数据的总线授权期间将组合的数据传送到数据总线。 当分配给总线授权的数据总线的带宽将由第一个数据填充时，设备在总线授权期间只将第一个数据传送到数据总线。

公开(公告)号：US20070009546A1

公开(公告)日：2007-01-11

申请号：US11403784

申请日：2006-04-13

Applicant: Michael Black ,  John Hodgson ,  David Knowles ,  Michael Lonetto ,  Richard Nicholas ,  Robert Stodola ,  Martin Burnham

Inventor： Michael Black ,  John Hodgson ,  David Knowles ,  Michael Lonetto ,  Richard Nicholas ,  Robert Stodola ,  Martin Burnham

IPC: A61K39/02 ,  C07H21/04 ,  C12P21/06 ,  C12N1/21 ,  C07K14/315

CPC classification number: C12N9/1077 ,  A61K38/00 ,  A61K39/00 ,  C07K14/3156 ,  C07K2319/00 ,  C12N9/1205 ,  C12N9/78 ,  C12N9/80 ,  C12Y207/01002

Abstract: The invention provides novel polypeptides and polynucleotides encoding such polypeptides and methods for producing such polypeptides by recombinant techniques. Also provided are methods for utilizing such polypeptides to screen for antibacterial compounds.

Abstract translation: 本发明提供了编码这种多肽的新型多肽和多核苷酸以及通过重组技术产生这种多肽的方法。 还提供了利用这些多肽筛选抗菌化合物的方法。

公开(公告)号：US20060143349A1

公开(公告)日：2006-06-29

申请号：US11021534

申请日：2004-12-23

Applicant: Richard Nicholas

Inventor： Richard Nicholas

IPC: G06F13/36

CPC classification number: G06F13/362

Abstract: A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

Abstract translation: 用于总线仲裁的电路布置，程序产品和方法改变了设备请求相对于彼此和先前仲裁序列被仲裁的顺序。 为此，仲裁器根据预定的顺序授予对第一组设备的访问。 仲裁器然后自动改变第二组设备的序列，根据改变的顺序授予对第二组总线的访问。 这些特征允许通过组的仲裁器序列相对于彼此自动变化的顺序，减少锁定的可能性。

公开(公告)号：US20060031743A1

公开(公告)日：2006-02-09

申请号：US10912483

申请日：2004-08-05

Applicant: Robert Dixon ,  Richard Nicholas ,  Kirk Morrow

Inventor： Robert Dixon ,  Richard Nicholas ,  Kirk Morrow

IPC: G06F11/00 ,  H03M13/00

CPC classification number: G06F11/1032

Abstract: A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

Abstract translation: 提供了一种方法，装置和计算机程序，用于顺序地确定存储的数据的奇偶性。 由于大多数内存阵列中存在固有的不稳定性，数据损坏可能是一个重大问题。 通常采用奇偶校验和其他技术来解决问题。 然而，通过奇偶校验和其他技术，有权衡。 例如，执行奇偶校验所需的时间可能会导致系统延迟。 因此，为了减少延迟，信任寄存器可以被包括在存储器系统中以允许立即访问一条可信数据。 通过能够读取一条可信赖的数据，系统可以通过从存储器阵列读取数据的下一个位置来重叠数据位置的奇偶校验和传送。 因此，可以消除整个周期的延迟，而不降低时钟频率。