公开(公告)号：US20120058736A1

公开(公告)日：2012-03-08

申请号：US13292501

申请日：2011-11-09

Applicant: Jan Roelof Westra ,  Rudy J. van de Plassche ,  Chi-Hung Lin

Inventor： Jan Roelof Westra ,  Rudy J. van de Plassche ,  Chi-Hung Lin

IPC: H04B1/44

CPC classification number: H04B1/583

Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract translation: 收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。 收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。 可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。 此外，高通滤波器和/或增益级也适于直接连接。 因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

公开(公告)号：US06324233B1

公开(公告)日：2001-11-27

申请号：US09120625

申请日：1998-07-22

Applicant: Adrianus Sempel ,  Eduard F. Stikvoort ,  Alphons A. M. L. Bruekers ,  Adrianus W. M. van den Enden ,  Rudy J. van de Plassche ,  Gerardus C. M. Gielis

Inventor： Adrianus Sempel ,  Eduard F. Stikvoort ,  Alphons A. M. L. Bruekers ,  Adrianus W. M. van den Enden ,  Rudy J. van de Plassche ,  Gerardus C. M. Gielis

IPC: H04B1400

CPC classification number: H04N5/4446 ,  H04B1/1036 ,  H04B1/26 ,  H04N5/4401 ,  H04N5/46

Abstract: In a receiver for receiving a modulated carrier (MC) having asymmetrical sidebands (USB,LSB), for example, a TV signal, a synchronous demodulator (SDEM) derives a vectorial baseband signal (VB) from the modulated carrier (MC). A filter (FILT) filters the vectorial baseband signal so as to compensate for the sideband asymmetry, for example, by means of a Nyquist slope. Thus, the sideband asymmetry is compensated at baseband frequencies, rather than at an intermediate frequency, which allows a better quality of reception.

Abstract translation: 在用于接收具有不对称边带（USB，LSB）的例如TV信号的调制载波（MC）的接收机中，同步解调器（SDEM）从调制载波（MC）导出矢量基带信号（VB）。 滤波器（FILT）对矢量基带信号进行滤波，以便例如通过奈奎斯特斜率补偿边带不对称性。 因此，边带不对称性在基带频率而不是中频处得到补偿，这允许更好的接收质量。

公开(公告)号：US5557275A

公开(公告)日：1996-09-17

申请号：US269812

申请日：1994-06-30

Applicant: Christinus J. van Valburg ,  Rudy J. van de Plassche

Inventor： Christinus J. van Valburg ,  Rudy J. van de Plassche

IPC: H03M1/12 ,  H03M7/00 ,  H03M7/16 ,  H03M1/36

CPC classification number: H03M7/165

Abstract: Encoder for the conversion of a signal of thermometric or cyclic type including a set of n Exclusive OR gates (X1, Xi, . . . , Xn) and an encoding matrix with n rows (1 . . . n) and a plurality of pairs of columns for a differential output of one bit of the binary signal, a matrix in which a row/column coupling is produced by a transistor (T). A pair of pseudo-columns of order zero is coupled to the rows in a way comparable to the coupling of the pair of columns of order 1, but by applying a cyclic shift in respect of the rank of the rows (rows of rank i of the pseudo-columns of order zero, coupled like the rows of rank (i modulo n)+1 of the columns of order 1). The bit of order zero [Bo] is obtained at the output of an additional Exclusive OR gate the inputs of which respectively receive the logic signal [Bo*] output by the pair of pseudo-columns of order zero, and the logic signal [B1] output by the pair of columns of order one.

Abstract translation: 用于转换包括一组n个异或门（X1，Xi，...，Xn）的温度测量或循环类型的信号的编码器和具有n行（...，）和多对的编码矩阵 用于二进制信号的一位的差分输出的列，其中由晶体管（T）产生行/列耦合的矩阵。 顺序为零的一对伪列以与订单1的列对的耦合相当的方式耦合到行，但是通过对行的等级（行的等级i应用循环移位） 顺序为零的伪列，与秩1的列（i模n）+ +1的行耦合。 在其输入分别接收由零对的一对伪列输出的逻辑信号[Bo *]和逻辑信号[B1（B））的附加异或门的输出处获得阶数零[Bo]的位 ]由一对订单列输出。

公开(公告)号：US5189422A

公开(公告)日：1993-02-23

申请号：US788410

申请日：1991-11-06

Applicant: Rudy J. van de Plassche ,  Petrus G. M. Baltus

Inventor： Rudy J. van de Plassche ,  Petrus G. M. Baltus

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/36

CPC classification number: H03M1/0602 ,  H03M1/365

Abstract: Analog-to-digital converter operating in parallel having an analog signal input and a number of digital signal outputs, comprising a plurality of comparators having each two inputs and one output, one input being connected to an impedance network for supplying this one input with its own predetermined reference voltage, and the second input being connected to the analog signal input for receiving an analog input signal to be converted, so that each of the comparators processes a predetermined input signal portion. The comparator outputs are coupled to corresponding digital signal outputs, while delay elements are inserted between the comparator outputs and the corresponding digital signal outputs for causing a delay to occur related to the steepness of the slope of the input signal portion of the relevant comparator.

公开(公告)号：US4517525A

公开(公告)日：1985-05-14

申请号：US445334

申请日：1982-11-29

Applicant: Eise C. Dijkmans ,  Rudy J. van de Plassche

Inventor： Eise C. Dijkmans ,  Rudy J. van de Plassche

IPC: H03F1/32 ,  H03F1/34 ,  H03F1/48 ,  H03F3/19 ,  H03F3/45 ,  H03F1/14

CPC classification number: H03F3/45071 ,  H03F1/48

Abstract: A differential amplifier with single-ended drive includes a balancing impedance (20) coupled between the base of the transistor (3) connected to the signal input (1) and the common point (9) of the two emitters of the transistors (3,4), which form a differential pair. The capacitance value of the capacitor (20) is substantially equal to the capacitance value of the stray capacitance (19) of the collector-substrate junction of a transistor (10) which forms a current source. This provides a symmetry of the capacitances between the input (1) and the common point (9) and between the common point (9) and ground via the transistor (10). This results in an improved balance in the output signals at the output terminals (5,6) and a flat frequency response of the differential amplifier for higher frequencies.

Abstract translation: 具有单端驱动的差分放大器包括耦合在连接到信号输入端（1）的晶体管（3）的基极和晶体管（3）的两个发射极的公共点（9）之间的平衡阻抗（20） 4），其形成差分对。 电容器（20）的电容值基本上等于形成电流源的晶体管（10）的集电极 - 衬底结的杂散电容（19）的电容值。 这提供了通过晶体管（10）在输入（1）和公共点（9）之间以及公共点（9）和接地之间的电容的对称性。 这导致在输出端子（5,6）处的输出信号的平衡得到改善，以及用于较高频率的差分放大器的平坦的频率响应。

公开(公告)号：US4325054A

公开(公告)日：1982-04-13

申请号：US62253

申请日：1979-07-30

Applicant: Rudy J. van de Plassche

Inventor： Rudy J. van de Plassche

IPC: G06G7/28 ,  H03K4/06 ,  H03K6/00 ,  H03M1/14 ,  H03M1/34 ,  H03M1/36 ,  H03M1/44 ,  H03K13/02

CPC classification number: H03K6/00 ,  G06G7/28 ,  H03K4/06 ,  H03M1/14 ,  H03M1/34 ,  H03M1/365 ,  H03M1/368

Abstract: In a folding circuit of an analog-to-digital converter a chain of emitters of transistors which are interconnected by threshold elements and fed by direct current sources are used to reduce the distortion. The circuit is controlled by a current source which produces the input signal.

Abstract translation: 在模数转换器的折叠电路中，使用由阈值元件互连并由直流电源馈送的晶体管的发射极链来减少失真。 该电路由产生输入信号的电流源控制。

公开(公告)号：US4280089A

公开(公告)日：1981-07-21

申请号：US088734

申请日：1979-10-26

Applicant: Rudy J. van de Plassche ,  Eise C. Dijkmans

Inventor： Rudy J. van de Plassche ,  Eise C. Dijkmans

IPC: G01R1/20 ,  H03G1/00 ,  H03H7/24 ,  H03H7/25 ,  H03H11/24 ,  G05F3/08

CPC classification number: G01R1/203 ,  H03G1/0088 ,  H03H11/24 ,  H03H7/24 ,  H03H7/25

Abstract: Attenuation arrangement comprising a step attenuator arranged in cascade with a controllable voltage divider via first and second voltage terminals, the step attenuator comprising a series arrangement of attenuation elements for dividing a voltage applied across said series arrangement into a plurality of voltage increments, which voltage increments are individually switchable between the two voltage terminals for varying the output voltage of the controllable voltage divider for the voltage range of the relevant voltage element, the direction of the polarity of the voltage between the two voltage terminals changing at a switch-over from one voltage increment to an adjacent voltage increment.

Abstract translation: 衰减布置包括通过第一和第二电压端子与可控分压器级联布置的步进衰减器，所述阶梯衰减器包括用于将施加在所述串联装置上的电压分成多个电压增量的衰减元件的串联布置，所述电压增量 可以在两个电压端子之间单独切换，用于在相关电压元件的电压范围内改变可控分压器的输出电压，两个电压端子之间的电压的极性方向从一个电压切换 增加到相邻的电压增量。

公开(公告)号：US4897656A

公开(公告)日：1990-01-30

申请号：US127867

申请日：1987-12-02

Applicant: Rudy J. van de Plassche ,  Peter G. Baltus

Inventor： Rudy J. van de Plassche ,  Peter G. Baltus

IPC: H03M1/12 ,  G06G7/30 ,  H03H17/00 ,  H03M1/14 ,  H03M1/20 ,  H03M1/36

CPC classification number: H03M1/205 ,  G06G7/30 ,  H03M1/141

Abstract: The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.

Abstract translation: 本发明围绕用于在多对互补主信号之间进行内插以产生另外的互补信号对的系统。 输入电路（10）提供主信号。 插值是一个两步操作。 第一步是用阻抗元件（R0-RN-1和RN0-RNN-1）的两个串（S和SN）完成。 每对主信号被提供给沿着串的一对相应的节点。 内插信号是沿着串的其他对相应节点取的。 在第二插值阶段，形成有附加阻抗元件（RD0-RDN-1和RDN0-RDNN-1）的延迟网络（D）通过构成串的阻抗元件来补偿传输延迟。

公开(公告)号：US4574270A

公开(公告)日：1986-03-04

申请号：US498617

申请日：1983-05-27

Applicant: Rudy J. van de Plassche

Inventor： Rudy J. van de Plassche

IPC: H03M1/20 ,  H03M1/44 ,  H03K13/09

CPC classification number: H03M1/445

Abstract: An analog-to-digital current converter comprises n series-connected stages which each provide one bit of the Gray code. For this purpose each stage m derives a difference current from the input current (i.sub.i/m), which is the output current (i.sub.0/m-1) of the preceding stage, and a reference current (I/2.sup.m-1) from a source (6). This difference current flows to the output (a) of the stage m (i.sub.o/m) either via a diode (3) or via a current (11) depending on its direction. Conduction of the diode (3) or of the current-mirror circuit (11) is used for the bit indication.This results in a very fast analog-to-digital converter with few components and a high accuracy and resolution.

Abstract translation: 模数转换器包括n个串联连接的级，每个级提供Gray码的一位。 为此，每个级m从与前一级的输出电流（i0 / m-1）和来自a的输入电流（i / 2m-1）的输入电流（I / 2m-1） 来源（6）。 该差电流通过二极管（3）或根据其方向通过电流（11）流到级m（io / m）的输出（a）。 二极管（3）或电流镜电路（11）的导通用于位指示。 这导致具有很少组件和高精度和高分辨率的非常快的模数转换器。

公开(公告)号：US4567426A

公开(公告)日：1986-01-28

申请号：US595062

申请日：1984-03-30

Applicant: Rudy J. van de Plassche ,  Peter J. M. Sijbers

Inventor： Rudy J. van de Plassche ,  Peter J. M. Sijbers

IPC: G05F3/30 ,  G05F1/56 ,  G05F3/26 ,  G05F3/16

CPC classification number: G05F3/265 ,  Y10S323/901

Abstract: Two current circuits are between two common terminals (+V.sub.B and -V.sub.B). The ratio between the currents in the two current circuits is defined by a first current-dividing circuit, and the absolute values of these currents are defined by means of a second current-dividing circuit, in particular a resistor in this second current-dividing circuit. In order to ensure that the current-stabilizing assumes the proper state upon activation, a first current-supply circuit is coupled to the input of the second current-dividing circuit, which current-supply circuit comprises the series arrangement of a resistor and a transistor arranged as a diode, and a second current-supply circuit is coupled to the output of the current-dividing circuit, which second current-supply circuit includes a transistor whose base is connected in common with that of the transistor of the first current-supply circuit.

Abstract translation: 两个公共端子（+ VB和-VB）之间有两个电流电路。 两个电流电路中的电流之间的比例由第一分流电路限定，这些电流的绝对值由第二分流电路，特别是该第二分流电路中的电阻器 。 为了确保电流稳定在启动时呈现适当的状态，第一电流供应电路耦合到第二分流电路的输入，该电流供应电路包括电阻器和晶体管的串联布置 被布置为二极管，第二电流供应电路耦合到分流电路的输出端，该第二电流源电路包括一个晶体管，其基极与第一电流源的晶体管的基极相连 电路。