公开(公告)号：US20240184458A1

公开(公告)日：2024-06-06

申请号：US18235678

申请日：2023-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Beomkyu Shin

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: A storage device includes at least one non-volatile memory including a plurality of blocks, each block of the plurality of blocks including a plurality of independently erasable sub-blocks. The storage device further includes a storage controller configured to select an erase mode from among a plurality of erase modes according to at least one of an operation schedule and a power consumption of the non-volatile memory, and control an erase operation of the non-volatile memory, according to the selected erase mode. Based on the selected erase mode being a first sub-block erase mode, the storage controller controls an erase operation with respect to one selected sub-block of a selected block. Based on the selected erase mode being a second sub-block erase mode, the storage controller controls an erase operation with respect to two or more selected sub-blocks of the selected block.

公开(公告)号：US11188415B2

公开(公告)日：2021-11-30

申请号：US16533905

申请日：2019-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomkyu Shin ,  Kui-Yon Mun ,  Sungkyu Park

IPC: G06F11/10 ,  G11C11/409 ,  G06F13/16 ,  G11C29/34 ,  G11C29/52

Abstract: A memory system includes a memory device including memory cells, and a controller that performs a write operation, a read operation, and a check operation on the memory device. During the check operation, the controller controls the memory device to read check data from target memory cells of the memory cells by using a check level, compares the check data with original data stored in the target memory cells, and determines a reliability of the target memory cells or the check data based on a result of the comparison.

公开(公告)号：US11144388B2

公开(公告)日：2021-10-12

申请号：US16506307

申请日：2019-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomkyu Shin ,  Sungkyu Park

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C29/42 ,  G11C11/56 ,  G11C16/10 ,  G11B20/18 ,  G11C13/00 ,  G11C7/10

Abstract: A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.

公开(公告)号：US11086745B2

公开(公告)日：2021-08-10

申请号：US16573101

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Jae-Yong Jeong ,  Sung-Kyu Park ,  Beomkyu Shin ,  Young-Seok Hong

IPC: G11C8/00 ,  G06F11/30 ,  G06F11/10 ,  G06F13/16 ,  G11C11/16 ,  G06F12/02

Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

公开(公告)号：US20210043240A1

公开(公告)日：2021-02-11

申请号：US16916345

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

公开(公告)号：US20200241989A1

公开(公告)日：2020-07-30

申请号：US16573101

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Jae-Yong Jeong ,  Sung-Kyu Park ,  Beomkyu Shin ,  Young-Seok Hong

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/16 ,  G06F12/02 ,  G11C11/16

Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

公开(公告)号：US20200183784A1

公开(公告)日：2020-06-11

申请号：US16506307

申请日：2019-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomkyu Shin ,  Sungkyu Park

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.