公开(公告)号：US08952517B2

公开(公告)日：2015-02-10

申请号：US13831367

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungkyu Kwon ,  JeongOh Ha

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15172 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided are a package-on-package device and a method of fabricating the same. In the device, solder balls may be disposed on two opposing side regions of a package substrate, such that the device can have a reduced size or width. In addition, input/output pads of the logic chip and the solder balls, which need to be directly connected to each other, can be disposed adjacent to each other. As a result, it is possible to improve routability of signals to and from the solder balls and to reduce the lengths of the interconnection lines. Accordingly, it is possible to reduce any signal interference, to increase signal delivery speed, and to improve signal-quality and power-delivery properties.

Abstract translation: 提供了一种封装封装器件及其制造方法。 在该器件中，焊球可以设置在封装衬底的两个相对的侧面区域上，使得该器件可以具有减小的尺寸或宽度。 此外，逻辑芯片的输入/输出焊盘和需要彼此直接连接的焊球可以彼此相邻地布置。 结果，可以提高信号到焊球和从焊球的路由性，并且减小互连线的长度。 因此，可以减少任何信号干扰，提高信号传递速度，并且改善信号质量和功率传送性能。

公开(公告)号：US11908810B2

公开(公告)日：2024-02-20

申请号：US17489328

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu Kwon ,  Junso Pak ,  Heeseok Lee

IPC: H01L23/16 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/16

Abstract: A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.

公开(公告)号：US11908758B2

公开(公告)日：2024-02-20

申请号：US17550284

申请日：2021-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu Kwon ,  Junso Pak ,  Heeseok Lee

IPC: H01L23/16 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/16 ,  H01L23/053 ,  H01L23/31

Abstract: A semiconductor package includes; a dual stiffener including an upper stiffener and a lower stiffener, an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate, and a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate.

公开(公告)号：US11244885B2

公开(公告)日：2022-02-08

申请号：US16573107

申请日：2019-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungkyu Kwon

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/18 ,  H01L25/065

Abstract: Disclosed is a semiconductor package system comprising a substrate, a first semiconductor package on the substrate, and a heat radiation structure on the first semiconductor package. The heat radiation structure includes a first part on a top surface of the first semiconductor package and a second part connected to the first part. The second part has a bottom surface at a level lower than a level of the top surface of the first semiconductor package. A vent hole is provided between an edge region of the substrate and the first part of the heat radiation structure.

公开(公告)号：US10068881B2

公开(公告)日：2018-09-04

申请号：US15392275

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu Kwon

IPC: H01L23/544 ,  H01L21/00 ,  H01L25/10 ,  H01L25/00

Abstract: Provided are a package-on-package type semiconductor package and a method of fabricating the same. The semiconductor package includes upper package stacked on a lower package and a via provided between the lower and upper packages to electrically connect the lower and upper packages to each other. The lower package includes a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer encapsulating the lower semiconductor chip and including an alignment mark. The lower mold layer includes a marking region, which is provided between the via and the lower semiconductor chip, and on which the alignment mark is provided.

公开(公告)号：US08981543B2

公开(公告)日：2015-03-17

申请号：US13951376

申请日：2013-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungkyu Kwon ,  Seungjin Cheon

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L23/28 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/565 ,  H01L23/13 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor packages are disclosed. In a semiconductor package, a package board may include a hole. A mold layer may cover an upper portion of the package board and extend through the hole to cover at least a portion of a bottom surface of the package board. Each of the sidewalls of a lower mold portion may have a symmetrical structure with respect to the hole penetrating the package board, such that a warpage phenomenon of the semiconductor package may be reduced.

Abstract translation: 公开了半导体封装。 在半导体封装中，封装板可以包括孔。 模具层可以覆盖封装板的上部并且延伸穿过孔以覆盖封装板的底表面的至少一部分。 下模具部分的每个侧壁可以具有相对于穿过封装板的孔的对称结构，从而可以减少半导体封装的翘曲现象。