公开(公告)号：US20190206800A1

公开(公告)日：2019-07-04

申请号：US15858103

申请日：2017-12-29

申请人： Intel IP Corporation

发明人： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/16227 ,  H01L2224/224 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161

摘要： An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

公开(公告)号：US09806017B2

公开(公告)日：2017-10-31

申请号：US14589578

申请日：2015-01-05

申请人： Tessera, Inc.

发明人： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/50 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1047 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/15151 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15172 ,  H01L2924/15182 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

摘要： A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

公开(公告)号：US09754924B2

公开(公告)日：2017-09-05

申请号：US15164296

申请日：2016-05-25

申请人： Apple Inc.

发明人： Chih-Ming Chung

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

摘要： Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

公开(公告)号：US09437586B2

公开(公告)日：2016-09-06

申请号：US14503575

申请日：2014-10-01

申请人： Min Gi Hong

发明人： Min Gi Hong

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/13 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/18 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/06134 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49097 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92127 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15172 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package.

摘要翻译： 提供一种半导体封装，其中单元阵列区域和外围电路区域分别形成为不同的半导体芯片。 包括存储单元的第一半导体芯片和仅包括第一半导体芯片公用的外围电路的第二半导体芯片彼此电连接。 因此，可以减小半导体封装的负载电容。 结果，可以减小半导体封装的RC延迟，从而提高半导体封装的工作速度。

公开(公告)号：US08975529B2

公开(公告)日：2015-03-10

申请号：US13638351

申请日：2011-03-25

申请人： Katsura Hayashi

发明人： Katsura Hayashi

IPC分类号： H05K1/11 ,  H05K1/16 ,  H05K7/06 ,  H05K1/02 ,  H01L23/498 ,  H01L23/14 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10342 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15172 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/00

摘要： There is provided an interposer which meets the need of improving electrical reliability of an electronic device. An interposer includes a substrate including a penetrating-hole in a thickness direction thereof, and a penetrating conductor disposed in the penetrating-hole. The substrate includes a first insulating layer and a second inorganic insulating layer which are separated from each other in the thickness direction, and a first resin layer interposed between the first inorganic insulating layer and the second inorganic insulating layer and being in contact with the first inorganic insulating layer and the second inorganic insulating layer. A coefficient of thermal expansion of the first resin layer in thickness and planar directions thereof is larger than those of the first inorganic insulating layer and the second inorganic insulating layer.

摘要翻译： 提供了一种内插器，其满足提高电子设备的电气可靠性的需要。 插入件包括在其厚度方向上包括穿透孔的基板和设置在贯通孔中的贯通导体。 基板包括在厚度方向上彼此分离的第一绝缘层和第二无机绝缘层，以及插入在第一无机绝缘层和第二无机绝缘层之间并与第一无机绝缘层接触的第一树脂层 绝缘层和第二无机绝缘层。 第一树脂层的厚度和平面方向的热膨胀系数大于第一无机绝缘层和第二无机绝缘层的热膨胀系数。

公开(公告)号：US20120267796A1

公开(公告)日：2012-10-25

申请号：US13306099

申请日：2011-11-29

申请人： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

发明人： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC分类号： H01L23/50

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1047 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/15151 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15172 ,  H01L2924/15182 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

摘要： A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

摘要翻译： 微电子组件可以包括具有第一和第二表面的基板和在其间延伸的孔，该基板具有端子。 组件还可以包括具有面向衬底的第一表面的前表面的第一微电子元件，具有面向第一微电子元件并且突出超过第一微电子元件的边缘的前表面的第二微电子元件，第一和第二引线电 将相应的第一和第二微电子元件的触点连接到端子，以及第三引线将第一和第二微电子元件的触点电互连。 第一微电子元件的触点可以在靠近其边缘的前表面暴露。 第二微电子元件的触点可以设置在其前表面的中心区域中。 第一，第二和第三引线可以具有与孔对准的部分。

公开(公告)号：US20080203583A1

公开(公告)日：2008-08-28

申请号：US12023761

申请日：2008-01-31

申请人： Gi-Jo Jung ,  In Soo Kang ,  Jong Heon Kim ,  Seung Dae Baek

发明人： Gi-Jo Jung ,  In Soo Kang ,  Jong Heon Kim ,  Seung Dae Baek

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/6835 ,  H01L22/10 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/83001 ,  H01L2224/85001 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15172 ,  H01L2924/15182 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production. After the semiconductor chips are formed at wafer level, only the semiconductor chips having the excellent operation characteristic through the test are selectively bonded to the multilayer thin film structure, to provide the high quality package products in which the fault rate is maximally reduced. The light, thin, short and small BGA package according to the present invention enables small and slim communication devices, displayers and other diverse electronic devices, to be contributed to the increase of the competitiveness of the products to which the BGA package is applied.

摘要翻译： 提供了一种半导体封装，包括：多层薄膜结构，其包括多个电介质层和至少一个或多个再分布层; 半导体芯片，其位于所述多层薄膜结构的一侧并电连接到所述再分配层; 以及形成在多层薄膜结构的另一侧的焊料凸块。 多层薄膜结构用作半导体封装的基板，实现轻，薄，短和小的BGA封装，而无需任何附加的基板。 可以在晶片级或载体级同时形成多个封装，以简化工艺并有利于批量生产。 半导体芯片在晶片级形成之后，仅通过测试具有优异的工作特性的半导体芯片选择性地结合到多层薄膜结构，从而提供故障率最大化降低的高品质封装产品。 根据本发明的轻，薄，短和小的BGA封装使小型和细长的通信设备，显示器和其他多种电子设备有助于提高应用BGA封装的产品的竞争力。

公开(公告)号：US12040315B2

公开(公告)日：2024-07-16

申请号：US17505594

申请日：2021-10-19

申请人： InnoLux Corporation

发明人： Jen-Hai Chi ,  Chia-Ping Tseng ,  Chen-Lin Yeh ,  Yan-Zheng Wu

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/07

CPC分类号： H01L25/072 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15172

摘要： An electronic device includes a carrier having at least one bonding pad, a plurality of electronic elements disposed on the carrier and one of the electronic elements including a substrate and at least one connecting terminal disposed between the substrate and the carrier. The electronic elements are electrically connected to the at least one bonding pad via the at least one connecting terminal.

公开(公告)号：US20180040544A1

公开(公告)日：2018-02-08

申请号：US15660718

申请日：2017-07-26

申请人： Invensas Corporation

发明人： Rajesh Emeka Katkar ,  Min Tao ,  Javier A. Delacruz ,  Hoki Kim ,  Akash Agrawal

IPC分类号： H01L23/498 ,  H05K3/34 ,  H05K1/18 ,  H05K1/11 ,  H01L25/10 ,  H01L21/48

CPC分类号： H01L23/49805 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49833 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/15172 ,  H01L2924/15331 ,  H01L2924/15333 ,  H05K1/117 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3405 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/09845 ,  H05K2201/10159 ,  H05K2201/10522

摘要： Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.

公开(公告)号：US20160268236A1

公开(公告)日：2016-09-15

申请号：US15164296

申请日：2016-05-25

申请人： Apple Inc.

发明人： Chih-Ming Chung

IPC分类号： H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

摘要： Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.