公开(公告)号：US09793291B2

公开(公告)日：2017-10-17

申请号：US15142365

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jin Shin ,  Hong-Suk Kim ,  Jung-Hwan Kim ,  Sang-Hoon Lee ,  Hun-Hyeong Lim ,  Yong-Seok Cho ,  Young-Dae Kim ,  Han-Vit Yang

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11568 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/0206 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

公开(公告)号：US20240145021A1

公开(公告)日：2024-05-02

申请号：US18236177

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong KIM ,  Hyun-Jin Shin

IPC: G11C29/12 ,  G11C7/08 ,  G11C29/46

CPC classification number: G11C29/1201 ,  G11C7/08 ,  G11C29/46

Abstract: A flash memory includes a first memory cell connected with a selected word line and a first bit line, a second memory cell connected with the selected word line and a second bit line, a sense amplifier that provides a sensing line with a sensing current for sensing data stored in the first memory cell or the second memory cell, a bit line selection circuit that selects a bit line by connecting the sensing line with the first bit line or the second bit line, and a margin read test circuit that performs a margin read test operation in which the margin read test circuit provides the sensing line with a margin current for testing a read margin of the data stored in the first memory cell or the second memory cell that is connected to the selected bit line.

公开(公告)号：US11722048B2

公开(公告)日：2023-08-08

申请号：US17560512

申请日：2021-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuseong Kim ,  Hyun-Jin Shin ,  Sanggyeong Won

IPC: H02M1/00 ,  G11C5/14 ,  H02M3/07

CPC classification number: H02M1/0045 ,  G11C5/145 ,  H02M3/07

Abstract: Provided a voltage generating circuits including assist circuits and operating methods thereof. The voltage generating circuit which includes an assist circuit that generates an assist signal indicating an enable mode or a disable mode. When a first power supply voltage is lower than an assist reference voltage, the assist signal indicates the enable mode, and a compensation circuit generates a compensation signal based on the first power supply voltage. An internal voltage converter generates a regulated voltage based on the first power supply voltage, and a charge pump circuit generates a pump voltage based on the regulated voltage. The compensation signal compensates for the regulated voltage.

公开(公告)号：US20220359004A1

公开(公告)日：2022-11-10

申请号：US17679530

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Gyeong Won ,  Gyu Seong Kim ,  Hyun-Jin Shin

IPC: G11C11/56 ,  G11C11/4074

Abstract: A non-volatile memory device is provided. The non-volatile memory device may include a memory cell array, a first pumping circuit configured to output a first pumping voltage, a second pumping circuit configured to pump the first pumping voltage of the first pumping circuit to output a second pumping voltage, and a pumping circuit control unit which is connected to the first pumping circuit and the second pumping circuit and configured to output at least one of the first pumping voltage and the second pumping voltage to the memory cell array. The first pumping circuit may be enabled in a first mode and a second mode different from the first mode, and the second pumping circuit may be disabled or not enabled in the first mode and enabled in the second mode.