Abstract:
An automatic test apparatus for embedded software and an automatic testing method thereof, the automatic testing apparatus for embedded software, includes an output detector which collects interface status information in accordance with data transmission/reception from at least one of first and second electronic devices respectively loaded with first and second embedded software and exchanging data therebetween, and extracts a keyword from the collected interface status information, a scenario composer which uses identification information about the first and second embedded software and the extracted keyword, and composes a scenario corresponding to a predetermined event status and a control command generator which generates a control command to reproduce the event status based on the composed scenario. Thus, it is possible to previously detect unpredictable and predictable problems that may occur in interaction between the plurality of embedded software, interface operation to transmit and receive data, etc., and reproduce them.
Abstract:
Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.
Abstract:
Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.
Abstract:
A first content output device (e.g., speaker) may include a communication interface, an output unit, and a processor. The first content output device, upon receiving a request, selectively transmits audio content to an external content output device (e.g., speaker) via two different networks. While the external content device is buffering the audio content received from the first content device via a first network, the devices are setting up for connection via a different second network. When the setting for connection between the device via the second network is completed, the first content output device switches to transmitting the audio content to the external content output device via the second network.
Abstract:
Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.
Abstract:
A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.
Abstract:
A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.
Abstract:
A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.
Abstract:
A nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer.