公开(公告)号：US20230396268A1

公开(公告)日：2023-12-07

申请号：US18055867

申请日：2022-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinsoo Lim ,  Changkyu Seol ,  Myoungbo Kwak ,  Pilsang Yoon

IPC: H03M13/09 ,  H03M13/11 ,  H03M13/45

CPC classification number: H03M13/09 ,  H03M13/1125 ,  H03M13/45

Abstract: Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.

公开(公告)号：US12170719B2

公开(公告)日：2024-12-17

申请号：US18379384

申请日：2023-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Young Jung ,  Jiyoup Kim ,  Changkyu Seol ,  Pilsang Yoon ,  Jinsoo Lim ,  Myunghoon Choi

IPC: H04L9/00 ,  G06F21/32 ,  H04L9/08 ,  G06F21/60

Abstract: An electronic device includes a memory storing data from an external source, an application processing unit (APU) transmitting a secret key and public key generation command, an isolated execution environment (IEE) generating a secret key in response to the secret key generation command, generating a public key based on the secret key in response to the public key generation command, and storing the secret key, and a non-volatile memory performing write and read operations depending on a request of the APU. When the data are stored in the memory, the APU transmits a public key request to the IEE and in response the IEE transfers the public key to the APU through a mailbox protocol. The APU generates a ciphertext by performing homomorphic encryption on the data based on an encryption key in the public key, and classifies and stores the public key and the ciphertext in the non-volatile memory.

公开(公告)号：US11468306B2

公开(公告)日：2022-10-11

申请号：US16906209

申请日：2020-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Hyejeong So ,  Hwaseok Oh ,  Pilsang Yoon ,  Jinsoo Lim

IPC: G06N3/063 ,  G06F15/80 ,  G06F7/544 ,  G06N3/08

Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.

公开(公告)号：US11335695B2

公开(公告)日：2022-05-17

申请号：US16710402

申请日：2019-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Byunggon Park ,  Joowon Park ,  Sangjun Hong ,  Jinsoo Lim

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L23/535

Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

公开(公告)号：US20210193678A1

公开(公告)日：2021-06-24

申请号：US16926045

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

公开(公告)号：US20240202067A1

公开(公告)日：2024-06-20

申请号：US18223124

申请日：2023-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghyeog CHOI ,  Changkyu Seol ,  Dong Kim ,  Inhoon Park ,  Jinsoo Lim ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A method of operating a storage device includes: periodically performing a patrol read operation on a memory device; storing failure information according to the patrol read operation in a buffer memory; generating an uncorrectable error as a result of a first error correction operation performed on read data of the memory device; loading the failure information from the buffer memory; and performing a second error correction operation on the read data by using the failure information.

公开(公告)号：US11757567B2

公开(公告)日：2023-09-12

申请号：US17590474

申请日：2022-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changkyu Seol ,  Jiyoup Kim ,  Hyejeong So ,  Myoungbo Kwak ,  Pilsang Yoon ,  Sucheol Lee ,  Jinsoo Lim ,  Youngdon Choi

IPC: H04L1/00 ,  G06F1/03

CPC classification number: H04L1/0041 ,  G06F1/03 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0084

Abstract: Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.

公开(公告)号：US20230032392A1

公开(公告)日：2023-02-02

申请号：US17934959

申请日：2022-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/48

Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

公开(公告)号：US11456316B2

公开(公告)日：2022-09-27

申请号：US16926045

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

IPC: H01L27/11582 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

公开(公告)号：US11411078B2

公开(公告)日：2022-08-09

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kiyoon Kang ,  Seogoo Kang ,  Shinhwan Kang ,  Jesuk Moon ,  Byunggon Park ,  Jaeryong Sim ,  Jinsoo Lim ,  Jisung Cheon ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.