中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

30 records (took 0.017 seconds)

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    11.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210134806A1

    公开(公告)日：2021-05-06

    申请号：US16903040

    申请日：2020-06-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H01L27/108

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    SEMICONDUCTOR DEVICE
    16.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240341086A1

    公开(公告)日：2024-10-10

    申请号：US18622473

    申请日：2024-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/09 ,  H10B12/50

    Abstract: An example semiconductor device includes a bit line structure and a bit line capping pattern that are stacked on a memory cell array region. The device further includes a peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked on a peripheral circuit region. The device further includes a gate spacer on a side surface of the peripheral gate structure, a first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer, and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer. The bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked. A material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer.

    Semiconductor device and a fabrication method thereof
    17.
    发明授权
    Semiconductor device and a fabrication method thereof 有权

    公开(公告)号：US11222897B2

    公开(公告)日：2022-01-11

    申请号：US16819920

    申请日：2020-03-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyesung Park ,  Jinwoo Bae ,  Youngho Koh ,  Jonghyuk Park ,  Boun Yoon ,  Myungjae Jang

    IPC: H01L27/108

    Abstract: A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

    SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250159867A1

    公开(公告)日：2025-05-15

    申请号：US18662164

    申请日：2024-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Donghoon Kwon ,  Jonghyuk Park

    IPC: H10B12/00 ,  H01L29/66

    Abstract: A semiconductor device includes an active pattern, a gate structure that extends in a first direction on the active pattern, a bit line electrically connected to the active pattern and extending in a second direction, a gate contact electrically connected to the gate structure, a dummy line between the gate contact and the bit line, and a dummy dielectric layer at least partially surrounded by the dummy line, where the dummy line includes: a first dummy line part between the dummy dielectric layer and the bit line, a second dummy line part spaced apart from the first dummy line part, and a plurality of connection parts that electrically connect the first and second dummy line parts to each other, and where the dummy dielectric layer is between the first dummy line part and the second dummy line part and is between the plurality of connection parts.

Patent Agency Ranking