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    SEMICONDUCTOR DEVICE
    14.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240341086A1

    公开(公告)日：2024-10-10

    申请号：US18622473

    申请日：2024-03-29

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon

    IPC分类号： H10B12/00

    CPC分类号： H10B12/482 ,  H10B12/09 ,  H10B12/50

    摘要： An example semiconductor device includes a bit line structure and a bit line capping pattern that are stacked on a memory cell array region. The device further includes a peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked on a peripheral circuit region. The device further includes a gate spacer on a side surface of the peripheral gate structure, a first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer, and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer. The bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked. A material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer.

    Semiconductor device and a fabrication method thereof
    15.
    发明授权
    Semiconductor device and a fabrication method thereof 有权

    公开(公告)号：US11222897B2

    公开(公告)日：2022-01-11

    申请号：US16819920

    申请日：2020-03-16

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hyesung Park ,  Jinwoo Bae ,  Youngho Koh ,  Jonghyuk Park ,  Boun Yoon ,  Myungjae Jang

    IPC分类号： H01L27/108

    摘要： A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

    SEMICONDUCTOR DEVICE
    18.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230030176A1

    公开(公告)日：2023-02-02

    申请号：US17662316

    申请日：2022-05-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yanghee Lee ,  Jonghyuk Park ,  Jinwoo Bae ,  Boun Yoon ,  Ilyoung Yoon

    IPC分类号： H01L27/108

    摘要： A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    19.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220344345A1

    公开(公告)日：2022-10-27

    申请号：US17859247

    申请日：2022-07-07

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC分类号： H01L27/108

    摘要： A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.