公开(公告)号：US11288356B2

公开(公告)日：2022-03-29

申请号：US16959834

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho Huh

IPC: G06F21/36 ,  G06F3/04883

Abstract: An electronic apparatus is disclosed. The electronic apparatus includes a display, and a processor configured to, based on a user command for setting unlocking information being input, display a screen including a word on the display, and store information on an object drawn on the screen by a user's gesture as the unlocking information, wherein the word is configured to induce an object related to the word to be drawn on the screen.

公开(公告)号：US20210350754A1

公开(公告)日：2021-11-11

申请号：US17244369

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changju Lee ,  Yongil Kwon ,  Yoon-Kyung Choi ,  Junho Huh

IPC: G09G3/34 ,  G09G5/10 ,  G09G3/32

Abstract: A backlight device includes LED elements divided into dimming groups; a panel driver configured to output a reference current for driving the LED elements; and pixel circuits, each of which is connected to the panel driver through a common line and is respectively configured to drive first LED elements comprised in a corresponding dimming group. Each of the pixel circuits is configured to: in a first period of a frame period, obtain a reference voltage based on the reference current and store the reference voltage, in a second period of the frame period, obtain luminance data of an image displayed by the corresponding dimming group, and in a third period of the frame period, drive the first LED elements during a light emitting time corresponding to the luminance data obtained in the second period using the reference voltage stored in the first period.

公开(公告)号：US20210065602A1

公开(公告)日：2021-03-04

申请号：US16996391

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changju LEE ,  Yoonkyung Choi ,  Jinbong Kim ,  Junho Huh

IPC: G09G3/20 ,  G06F3/041 ,  G06K9/00 ,  A61B5/00

Abstract: A display chipset structure that is based on an integrated display controller is provided. The display controller includes including a display processor comprising a first digital circuit, and configured to receive image data from an application processor (AP) and output the image data to a first component driver chip configured to drive a gate line and a source line of a display panel; and a touch processor comprising a second digital circuit, and configured to receive touch data from a second component driver chip configured to drive sensing electrodes of a touch panel. The display controller is implemented as one semiconductor chip and separated from each of the first and second component driver chips, and the display processor and the touch processor communicate with each other through an internal interconnection of the one semiconductor chip.

公开(公告)号：US10133692B2

公开(公告)日：2018-11-20

申请号：US15190629

申请日：2016-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho Huh ,  Horang Jang ,  Tomas Scherrer ,  Jaewon Lee

IPC: G06F13/16 ,  G06F13/36 ,  G06F13/42 ,  G11C8/10 ,  G11C7/10 ,  G11C7/22

Abstract: A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.

公开(公告)号：US20250159342A1

公开(公告)日：2025-05-15

申请号：US19025367

申请日：2025-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong Kim ,  Dongook Chung ,  Junho Huh

IPC: H04N23/60 ,  G06T7/20 ,  H04N23/611 ,  H04N23/65 ,  H04N23/667

Abstract: A sensor includes a control circuit set to a first operation mode in which an operation is prepared by receiving a clock signal from a processor and receiving an operation command from the processor. The sensor is configured to generate a first signal including a result of an operation corresponding to the operation command and a second signal indicating completion of the operation. An interface circuit is configured to transmit the first signal and the second signal to the processor. The control circuit is set to a second operation mode due to blocking of the clock signal by a control of the processor in response to the transmission of the second signal.

公开(公告)号：US11734067B2

公开(公告)日：2023-08-22

申请号：US16789602

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Min Kim ,  Byungchul Jeon ,  Junho Huh

IPC: G06F9/48 ,  G06F9/50 ,  G06F1/3287 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/4893 ,  G06F1/3287 ,  G06F9/505 ,  G06F11/3024 ,  G06F11/3423 ,  G06F2209/486

Abstract: In a method of operating a multi-core system comprising a plurality of processor cores, a plurality of task stall information respectively corresponding to a plurality of tasks are provided by monitoring a task stall time with respect to each task. The task stall time indicates a time while the each task is suspended within a task active time, and the task active time indicates a time while a corresponding processor core is occupied by the each task. Task scheduling is performed based on the plurality of task stall information, and a fine-grained dynamic voltage and frequency scaling (DVFS) is performed based on the task scheduling. The plurality of tasks may be assigned to the plurality of processor cores based on load unbalancing, and the effects of the fine-grained DVFS may be increased to reduce the power consumption of the multi-core system.

公开(公告)号：US11552801B2

公开(公告)日：2023-01-10

申请号：US16790243

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghyun Kim ,  Junho Huh

IPC: H04L9/32 ,  G06F3/06 ,  G06F21/55

Abstract: In a method of operating a memory system, first security data and a first timestamp for preventing a replay attack are written by a host device to a first memory area which is an external memory area. A second timestamp is updated by the host device based on the first timestamp. The second timestamp corresponding to the first timestamp is stored in a second memory area distinguished from the first memory area. A first notification signal representing a result of updating the second timestamp is received by the host device. A writing operation for the first security data is completed when it is determined, by the host device, based on the first notification signal that the second timestamp is successfully updated.

公开(公告)号：US11436176B2

公开(公告)日：2022-09-06

申请号：US16734844

申请日：2020-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsoo Lee ,  Jaewon Lee ,  Junho Huh ,  Helin Lin

IPC: G06F13/40 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/42

Abstract: A semiconductor integrated circuit includes a central processing unit, a hardware function block that outputs a plurality of hardware signals to be transmitted to an external device independently of the central processing unit, a virtual general purpose input/output (GPIO) finite state machine that transforms the plurality of hardware signals to a virtual GPIO payload, and an I3C communication block that transmits the virtual GPIO payload to the external device through a serial data line and a serial clock line.

公开(公告)号：US11323265B2

公开(公告)日：2022-05-03

申请号：US16698093

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjick Lee ,  Sunghyun Kim ,  Junho Huh

IPC: H04L9/32 ,  G11C17/14 ,  H04L9/08

Abstract: A storage device includes a basic memory to store a message received from an external device, a security memory to store an authentication key for authenticating the message, a controller to output a control signal, and a security engine to obtain the authentication key from the security memory with an authority to access the security memory in response to the control signal from the controller and to block an access of the controller to the security memory.

公开(公告)号：US11275394B2

公开(公告)日：2022-03-15

申请号：US17027946

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minshik Seok ,  Younghoon Lee ,  Kyungrae Kim ,  Kyungsoo Lee ,  Junho Huh

IPC: G05F1/56 ,  G06F1/26

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.