公开(公告)号：US20230052161A1

公开(公告)日：2023-02-16

申请号：US17873739

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Seok ,  Younggul Song ,  Eunchu Oh ,  Byungchul Jang ,  Joonsung Lim

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

公开(公告)号：US12154646B2

公开(公告)日：2024-11-26

申请号：US17816601

申请日：2022-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Seok ,  Younggul Song ,  Eunchu Oh

IPC: G11C29/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C29/50

Abstract: In a method of reprogramming data in a nonvolatile memory device including a plurality of pages each of which includes a plurality of memory cells, first page data programmed in a first page is read from among a plurality of page data programmed in the plurality of pages. The plurality of page data have a threshold voltage distribution including a plurality of states. An error correction code (ECC) decoding is performed on the first page data. A reprogram operation is selectively performed on target bits in which an error occurs among a plurality of bits included in the first page data based on a result of performing the ECC decoding on the first page data and a reprogram voltage. The target bits correspond to a first state among the plurality of states. A voltage level of the reprogram voltage is adaptively changed.

公开(公告)号：US12125534B2

公开(公告)日：2024-10-22

申请号：US17935122

申请日：2022-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggul Song ,  Junyeong Seok ,  Eun Chu Oh ,  Byungchul Jang

IPC: G11C8/00 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B69/00

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H10B69/00

Abstract: A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

公开(公告)号：US20230154537A1

公开(公告)日：2023-05-18

申请号：US17935122

申请日：2022-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGGUL SONG ,  Junyeong Seok ,  Eun Chu Oh ,  Byungchul Jang

IPC: G11C16/04 ,  G11C16/08 ,  H01L27/115 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H01L27/115

Abstract: A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

公开(公告)号：US20230141554A1

公开(公告)日：2023-05-11

申请号：US18053850

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUN CHU OH ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0673 ,  G06F3/0644

Abstract: A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N−K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N−K logical pages, wherein K is a positive integer and N is a positive integer greater than K.

公开(公告)号：US20230118956A1

公开(公告)日：2023-04-20

申请号：US18047270

申请日：2022-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggul Song ,  Junyeong Seok ,  Eun chu OH ,  Minho Kim ,  Byungchul Jang

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/08

Abstract: A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.

公开(公告)号：US20230111033A1

公开(公告)日：2023-04-13

申请号：US17749691

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

Abstract: A storage device, including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array including a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes, and a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells into outer cells and inner cells. The storage controller includes an error correction code (ECC) decoder configured to perform an ECC decoding operation by obtaining outer cell bits and inner cell bits during a read operation on the plurality of target memory cells, and applying different log likelihood ratio (LLR) values to the outer cell bits and the inner cell bits.