公开(公告)号：US20210359200A1

公开(公告)日：2021-11-18

申请号：US17110524

申请日：2020-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Kohji KANAMORI ,  Unghwan PI ,  Hyuncheol KIM ,  Sungwon YOO ,  Jaeho HONG

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01L23/522

Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.

公开(公告)号：US20210049340A1

公开(公告)日：2021-02-18

申请号：US16806011

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Daekwan Kim ,  Yohwan Noh

IPC: G06K9/00 ,  G02B3/00

Abstract: An electronic device includes a substrate, a plurality of light sources, the plurality of light sources configured to emit an optical signal to an object through the substrate, at least one sensor underneath the substrate, the at least one sensor configured to detect biometric information associated with the object by receiving a reflected light signal, the reflected light signal corresponding to the optical signal reflected off the object and transferred through the substrate, and a multi-lens array including at least one support layer, a plurality of first lenses, and a plurality of second lenses, the at least one support layer in an upper portion of the at least one sensor, the plurality of first lenses on an upper surface of the at least one support layer, and the plurality of second lenses on a lower surface of the at least one support layer.

公开(公告)号：US20250132589A1

公开(公告)日：2025-04-24

申请号：US19007551

申请日：2025-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwoo KANG ,  Kyunghwan LEE

IPC: H02J7/00

Abstract: An electronic device according to various embodiments of the disclosure may include a first charging circuit connected to a first node and a second node, a second charging circuit connected to the first node and a third node, a switch connected to the second node and the third node, a battery connected to the second node, a system circuit connected to the third node, and a processor. In addition, various embodiments may be possible.

公开(公告)号：US20240422964A1

公开(公告)日：2024-12-19

申请号：US18421187

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Wonsok LEE ,  Juho LEE ,  Daewon HA

IPC: H10B12/00 ,  H01L29/10

Abstract: A semiconductor memory device includes a memory cell array having a three-dimensional structure, the memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction are perpendicular to each other, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, wherein each of the plurality of memory cells includes two transistors including at a least portions of two word lines passing through the memory cell in the vertical direction and at least portions of two bit lines respectively on both sides of the two word lines in the first lateral direction, each of the two bit line extending along the second lateral direction, and each of the plurality of memory cells does not include a capacitor.

公开(公告)号：US20240266287A1

公开(公告)日：2024-08-08

申请号：US18457907

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Daewon HA

IPC: H01L23/528 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20

CPC classification number: H01L23/5283 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20

Abstract: A semiconductor device may include first conductive lines spaced apart from each other in a first direction on a substrate, second conductive lines spaced apart from the first conductive lines in a second direction, a gate electrode between the first and second conductive lines and extending in the first direction, a first selection gate electrode between the first conductive lines and the gate electrode and extending in the first direction, a plurality of channel patterns surrounding a side surface of the gate electrode and spaced apart from each other in the first direction, a plurality of first selection channel patterns surrounding a side surface of the first selection gate electrode and a ferroelectric pattern between the gate electrode and each of the channel patterns. The first selection channel patterns may be spaced apart from each other in the first direction and connected to the channel patterns, respectively.

公开(公告)号：US20240164108A1

公开(公告)日：2024-05-16

申请号：US18235000

申请日：2023-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Daewon HA

IPC: H10B51/20 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: A three-dimensional ferroelectric memory device includes a channel on a substrate and extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a gate insulation pattern and a conductive pattern stacked on and surrounding a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate, a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern, a gate electrode contacting the ferroelectric pattern, and first and second source/drain patterns contacting lower and upper surfaces, respectively, of the channel.

公开(公告)号：US20230307448A1

公开(公告)日：2023-09-28

申请号：US17950434

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Sungil PARK ,  Jae Hyun PARK ,  Daewon HA

IPC: H01L27/06 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/785

Abstract: A three-dimensional semiconductor device comprises a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a first active contact electrically connected to the lower source/drain pattern, an upper separation structure between the first active contact and the upper source/drain pattern, a second active contact electrically connected to the upper source/drain pattern, and a lower separation structure between the second active contact and the lower source/drain pattern.

公开(公告)号：US20230247340A1

公开(公告)日：2023-08-03

申请号：US18102426

申请日：2023-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE

IPC: H04R1/10

CPC classification number: H04R1/1016 ,  H04R2460/11

Abstract: An example earphone includes a housing having a speaker module embedded therein and an ear tip connected to the housing. The housing includes a coupling portion having a sound hole formed in an end portion thereof. The ear tip includes a first tip including a first hollow aligned with the sound hole in a first direction and a first sidewall that surrounds the first hollow and a second tip including a second hollow in which the first tip is accommodated and a second sidewall that surrounds the second hollow, the first direction being a direction toward the speaker module from the sound hole. The first tip includes a first connecting portion having a protrusion form on an end portion thereof in the first direction. The coupling portion includes, on one surface thereof, a second connecting portion including a groove with which the first connecting portion is engaged. A connection gap is formed between facing surfaces of the first connecting portion and the second connecting portion, and the coupling portion of the housing and the ear tip are connected so as to be rotatable relative to each other.

公开(公告)号：US20230024307A1

公开(公告)日：2023-01-26

申请号：US17590087

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO

IPC: H01L27/11507

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a substrate; a transistor disposed above the substrate, the transistor having a channel region defining an inner space; and a capacitor passing through the transistor in a vertical direction in the inner space.

公开(公告)号：US20220367479A1

公开(公告)日：2022-11-17

申请号：US17716215

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Dongsoo WOO ,  Sungwon YOO

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/792

Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.