Semiconductor memory device
    14.
    发明授权

    公开(公告)号:US11521977B2

    公开(公告)日:2022-12-06

    申请号:US17471824

    申请日:2021-09-10

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    SEMICONDUCTOR MEASUREMENT APPARATUS
    17.
    发明公开

    公开(公告)号:US20230400404A1

    公开(公告)日:2023-12-14

    申请号:US18154990

    申请日:2023-01-16

    CPC classification number: G01N21/21 G01B11/24 G01B2210/56

    Abstract: A semiconductor measurement apparatus includes an illumination unit including a light source and at least one illumination polarization element, a light receiving unit including at least one light-receiving polarization element disposed on a path of light reflected by a sample, and an image sensor positioned to receive light passing through the at least one light-receiving polarization element and configured to output an original image, and a control unit configured to determine, by processing the original image, a selected critical dimension among critical dimensions of a structure included in a region of the sample. The control unit is configured to obtain a plurality of sample images by selecting regions of the original image in which a peak due to interference appears, to determine a plurality of elements included in a Mueller matrix using the plurality of sample images, and to determine the selected critical dimension based on the plurality of elements.

    PLASMA ETCHING APPARATUS AND SEMICONDUCTOR PROCESSING SYSTEM

    公开(公告)号:US20230078095A1

    公开(公告)日:2023-03-16

    申请号:US17695062

    申请日:2022-03-15

    Abstract: A plasma etching apparatus includes a housing having a processing space; a support inside the housing, the support configured to support a substrate and including at least one lower electrode; at least one upper electrode facing the at least one lower electrode; a sidewall electrode disposed on a sidewall of the housing; a lower radiofrequency (RF) power source connected to the at least one lower electrode and configured to apply RF power; an upper RF power source connected to the at least one upper electrode and configured to apply RF power; a lower insulator adjacent to the at least one lower electrode; an upper insulator adjacent to the at least one upper electrode; at least one lower detector embedded in the lower insulator; and at least one upper detector embedded in the upper insulator.

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